A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters

Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter （SA-ADC） are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

Mine-used multi-function serial signal converter based on Ethernet

A mine-used multi-function serial signal converter is introduced.This converter is based on Ethernet.The core of this design is embedded microprocessor STM32F107VCT6.Embedded operation system μC/OS-Ⅱ is transplanted into this converter,and light-weight Internet protocal （LwIP） stack is also embedded to realize mutual conversion of serial signals such as meter bus （M-Bus） signal,RS485 signal,RS232 signal and Ethernet signal.Interconnection between all kinds of monitoring system interfaces under coal mine can be formed easily,which can solve compatibility problem between monitoring system and communication system and improve overall performance of safety monitoring system.The designed multi-function serial signal converter is of great value for application,which is worthy to be popularized in coal mine safety production.

A Novel Serial Hybrid Three-level NPC Topology for Multi-MW Medium Voltage Wind Power Converters

提出一种新型的串联混合三电平中点钳位（neutralpoint clamped,NPC）拓扑,该拓扑是基于传统三电平NPC拓扑的改进和优化,引入大功率IGBT的串联应用。该新型拓扑中,桥臂的两个外管分别用两个低压IGBT串联,两个内管均用高压IGBT。在多兆瓦级中压风电变流器中,大功率IGBT的开关损耗很大,从而限制了开关频率。提出的新型拓扑通过低压IGBT的串联来减小功率器件的损耗,从而提高开关频率,同时可减小输出滤波器的尺寸。通过传统三电平拓扑和新型串联混合三电平拓扑IGBT损耗的对比,说明新拓扑的优势。通过改变门极驱动电阻实现串联IGBT的均压,对新拓扑的应用具有重大意义。最后通过新拓扑的单相样机验证新拓扑的正确性和可行性。

A 71mW 8b 125MSample/s A/D Converter

A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.

A 1.8V 10bit 100Msps Pipelined Analog to Digital Converter

A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch ＂on＂ resistance. With the gain-boost technology,the operational transconductance amplifier used in this analog-to-digital converter （ADC） achieves enough DC gain and unity-gain frequency under the low voltage supply and to guarantee the performance of the sample and hold circuit （S/H） and the sub-stages. Based on these methods,a 10bit 100Msps pipelined ADC is fabricated in a 0. 18μm CMOS process and operates under a 1.8V voltage supply. The ADC achieves an SNR of 54. 2dB （input frequency of 6.26MHz） and an SNR of 49. 8dB （input frequency of 48. 96MHz） when the sampling frequency is 100MHz.

200Ms/s 177mW 8bit Folding and Interpolating CMOS A/D Converter

A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.

Design of a 14-Bit 1 MS/s Successive Approximation Analog-to-Digital Converter

A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.

基于累加式实时串并联变换算法的机械故障声学监测方法

针对基于物联网(IoT)的冲压机床故障监测问题,为了降低冲压机床故障监测的计算复杂度,并提高其低频识别的精度,提出了一种无需机器学习技术的实时性机械故障声学监测方法,即基于累加式实时串并联变换算法的机械故障声学监测方法。首先,研究了物联网场景中冲压机床声学低频分析的必要性,并给出了声学信号的表达式;然后,针对频率轴上多个周期信号重叠导致参数估计较为困难的问题,提出了一种累加式实时串并联变换算法,将输入的采样序列馈入多个具有不同输出端口的串并转换器,从累加的波形中检测出最大绝对值,并进行了比较;最后,通过样本时隙划分,将累加式实时串并联变换算法应用于机械故障监测;通过仿真和冲压机床实机测试,对累加式实时串并联变换算法和实时性机械故障声学监测方法的有效性进行了验证。研究结果表明:在无需大量信号样本的情况下,使用累加式实时串并联变换算法有利于提高低频带的识别精度;在直方图相关性方面,累加式实时串并联变换算法和Morlet小波变换具有相同的性能,且均明显优于短时傅立叶变换;同时,尽管累加式实时串并联变换算法需要的加法总数比Morlet小波变换多2.5倍,但是乘法总数减少了20447%,大幅减少了计算的复杂度。

西门子PLC与丹佛斯变频器的通讯技术在造纸机变频传动控制系统中的应用

介绍了基于西门子S7-300 PLC与丹佛斯变频器的通讯技术在造纸机变频传动控制系统中的应用。PLC的CP340通讯模块与变频器通过RS485接口实现通讯,组成控制网络。整个系统控制精度高,实时性好,使用效果好。

串行通信技术在变频器上应用的重要作用

在我国科技快速发展的背景下,工业领域也在高速发展,目前许多企业为实现智能化制造,在电气控制元件上预留了通信接口,这样一来就可以在变频器上应用串行通信技术,实现不同设备之间的网络通信。但是要想实现串行通信,还需要在变频器中对频率、电压进行调整。基于此,文章先简要阐述串行通信技术,然后分析如何利用串行通信技术实现变频器与可编程控制器之间的网络通信,希望能够为我国网络技术的发展提供有效帮助。

Stability optimization of channel-interleaved photonic analog-to-digital converter by extracting of dual-output photonic demultiplexing

We investigate a channel-interleaved photonic analog-to-digital conversion(PADC)system’s ability to work stably over a long duration with an optimal driving voltage.The influence of optimum bias point drift of a Mach–Zehnder modulator(MZM)-based photonic switch on this system was analyzed theoretically and experimentally.The feasibility of extracting feedback signals from the PADC system was derived.A high-stability channel-interleaved PADC was constructed by extracting a feedback signal from a parallel demultiplexing module to control the MZM-based photonic switch’s driving voltage.Consequently,the amplitude mismatch between the channels was limited to within 0.3 d B over 12 hours of operation.

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

A 12-bit 250-MS/s Charge-Domain Pipelined Analog-to-Digital Converter with Feed-Forward Common-Mode Charge Control

A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.

Switching response of dual-output Mach–Zehnder modulator in channel-interleaved photonic analog-to-digital converter

This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A figure of merit(FoM) is introduced to evaluate the switching response of the PADC when a dual-output Mach–Zehnder modulator(MZM) serves as the photonic switch to parallelize the sampled pulse train into two channels. After the optimization of the FoM and utilization of the channel-mismatch compensation algorithm,the system bandwidth of PADC is expanded and the signal-to-distortion ratio is enhanced.