The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of...The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.展开更多
A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a h...A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a half-rate four-tap decision feedback equalizer （DFE）. The equalizer used the Signsign least mean-squared （SS-LMS） algorithm to realize the coefficient adaptation. An automatic gain control （AGC） amplifier with the sign least mean-squared （S-LMS） algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery （BB-CR） is adopted. A third order phase loop loek （PLL） model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34＂ FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.展开更多
文摘The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.
基金Supported by the High Technology Research and Development Programme of China (No. 2003AA31g030).
文摘A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a half-rate four-tap decision feedback equalizer （DFE）. The equalizer used the Signsign least mean-squared （SS-LMS） algorithm to realize the coefficient adaptation. An automatic gain control （AGC） amplifier with the sign least mean-squared （S-LMS） algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery （BB-CR） is adopted. A third order phase loop loek （PLL） model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34＂ FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.
