期刊文献+
共找到2篇文章
< 1 >
每页显示 20 50 100
Trichloroethylene Induces Biphasic Concentration-dependent Changes in Cell Proliferation and the Expression of SET-Associated Proteins in Human Hepatic L-02 Cells 被引量:1
1
作者 HONG Wen Xu YE Jin Bo +10 位作者 CHEN Mou Tong YAN Yan ZHOU Gui Feng YANG Xi Fei YANG Liang REN Xiao Hu HUANG Hai Yan ZHOU Li HUANG Xin Feng ZHUANG Zhi Xiong LIU Jian Jun 《Biomedical and Environmental Sciences》 SCIE CAS CSCD 2013年第7期618-621,共4页
Trichloroethylene (TCE) is a major pollutant that affects both occupational and general environments. The liver is an important target organ of TCEE. Substantial efforts and remarkable progress into understanding TC... Trichloroethylene (TCE) is a major pollutant that affects both occupational and general environments. The liver is an important target organ of TCEE. Substantial efforts and remarkable progress into understanding TCE cytotoxicity have been made in cultured liver cells. However, the molecular mechanisms by which TCE induces hepatotoxicity are not well understood. SET (also known as protein phosphatase 2A inhibitor, 12PP2A, or template-activating factor-I, TAF-D is a nuclear protein that regulates histone modification, gene transcription, DNA replication, nucleosome assembly, 展开更多
关键词 SET As TCE Trichloroethylene Induces Biphasic Concentration-dependent Changes in Cell Proliferation and the Expression of set-associated Proteins in Human Hepatic L-02 Cells
下载PDF
Dual-Port Content Addressable Memory for Cache Memory Applications
2
作者 Allam Abumwais Adil Amirjanov +1 位作者 Kaan Uyar Mujahed Eleyat 《Computers, Materials & Continua》 SCIE EI 2022年第3期4583-4597,共15页
Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual... Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory(DPCAM).In addition,it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm(NFRA)to reduce the cost overhead of the cache controller and improve the cache access latency.The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory.Moreover,it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM.However,an estimation of the power dissipation showed that DPCAM consumes about 7%greater than a set-associative cache memory of the same size.These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory. 展开更多
关键词 Multicore system content addressable memory dual port CAM cache controller set-associative cache power dissipation
下载PDF
上一页 1 下一页 到第
使用帮助 返回顶部