Currently,the mainstream vector network analyzer employs embedded computer module with a digital intermediate frequency(IF)board to form a high performance windows platform.Under this structure,the vector network anal...Currently,the mainstream vector network analyzer employs embedded computer module with a digital intermediate frequency(IF)board to form a high performance windows platform.Under this structure,the vector network analyzer needs a powerful encoding system to arbitrate the bus acquirement,which is usually realized by field-programmable gate array(FPGA)chip.The paper explores the shared bus design method of the digital signal processing(DSP)board in network analyzer.Firsty,it puts an emphasis on the system structure,and then the shared bus communication method is described in detail;Finally,the advantages of the shared bus communication mechanism are summanzed.展开更多
A series-parallel system was proposed with common bus performance sharing in which the performance and failure rate of the element depended on the load it was carrying. In such a system,the surplus performance of a su...A series-parallel system was proposed with common bus performance sharing in which the performance and failure rate of the element depended on the load it was carrying. In such a system,the surplus performance of a sub-system can be transmitted to other deficient sub-systems. The transmission capacity of the common bus performance sharing mechanism is a random variable. Effects of load on element performance and failure rate were considered in this paper. A reliability evaluation algorithm based on the universal generating function technique was suggested. Numerical experiments were conducted to illustrate the algorithm.展开更多
文摘Currently,the mainstream vector network analyzer employs embedded computer module with a digital intermediate frequency(IF)board to form a high performance windows platform.Under this structure,the vector network analyzer needs a powerful encoding system to arbitrate the bus acquirement,which is usually realized by field-programmable gate array(FPGA)chip.The paper explores the shared bus design method of the digital signal processing(DSP)board in network analyzer.Firsty,it puts an emphasis on the system structure,and then the shared bus communication method is described in detail;Finally,the advantages of the shared bus communication mechanism are summanzed.
基金National Natural Science Foundations of China(Nos.71231001,11001005,71301009)China Postdoctoral Science Foundation(No.2013M530531)+1 种基金the Fundamental Research Funds for the Central Universities of China(Nos.FRF-M P-13-009A,FRF-TP-13-026A)the MOE PhD Supervisor Fund of China(No.20120006110025)
文摘A series-parallel system was proposed with common bus performance sharing in which the performance and failure rate of the element depended on the load it was carrying. In such a system,the surplus performance of a sub-system can be transmitted to other deficient sub-systems. The transmission capacity of the common bus performance sharing mechanism is a random variable. Effects of load on element performance and failure rate were considered in this paper. A reliability evaluation algorithm based on the universal generating function technique was suggested. Numerical experiments were conducted to illustrate the algorithm.
