GeSi Source/Drain Structure for Suppression of Short Channel Effect in SOI p-MOSFET's

GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold voltage rolling off and DIBL effect is thoroughly investigated,as well as the influence of the Ge concentration and silicon film thickness.The Ge concentration should be carefully chosen as a tradeoff between the driving current and SCE improvement.The detailed physics is explained.

New aspects of HCI test for ultra-short channel n-MOSFET devices

Hot carriers injection （HCI） tests for ultra-short channel n-MOSFET devices were studied. The experimental data of short channel devices （75-90 nm）, which does not fit formal degradation power law well, will bring severe error in lifetime prediction. This phenomenon usually happens under high drain voltage （Vd） stress condition. A new model was presented to fit the degradation curve better. It was observed that the peak of the substrate current under low drain voltage stress cannot be found in ultra-short channel device. Devices with different channel lengths were studied under different Vd stresses in order to understand the relations between peak of substrate current （/sub） and channel length/stress voltage.

The Bipolar Field-Effect Transistor: III.Short Channel Electrochemical Current Theory (Two-MOS-Gates on Pure-Base)

This paper describes the short channel theory of the bipolar field-effect transistor （BiFET） by partitioning the transistor into two sections,the source and drain sections,each can operate as the electron or hole emitter or collector under specific combinations of applied terminal voltages. Analytical solution is obtained in the source and drain sections by separating the two-dimensional trap-free Shockley Equations into two one-dimensional equations parametrically coupled via the surface-electric-potential and by using electron current continuity and hole current continuity at the boundary between the emitter and collector sections. Total and electron-hole-channel components of the output and transfer currents and conductances, and the electrical lengths of the two sections are computed and presented in graphs as a function of the D. C. terminal voltages for the model transistor with two identical and connected metal-oxide-silicon-gates （MOS-gates） on a thin pure-silicon base over practical ranges of thicknesses of the silicon base and gate oxide. Deviations of the long physical channel currents and conductances from those of the short electrical channels are reported.

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack(TMGS) DG-MOSFET

In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.

Development of Physical Library for Short Channel CMOS / SOI Integrated Circuits

An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used for design and fabrication and physical library development of thin film submicron and deep submicron CMOS/ SOI integrated circuit.

Shot Noise Suppression in a Quantum Point Contact with Short Channel Length

An experimental study on the current shot noise of a quantum point contact with short channel length is reported. The experimentally measured maximum energy level spacing between the ground and the first excited state of the device reached up to 7.5meV, probably due to the hard wall confinement by using shallow electron gas and sharp point contact geometry. The two-dimensionM non-equilibrium shot noise contour map shows noise suppression characteristics in a wide range of bias voltage. Fano factor analysis indicates spin-polarized transport through a short quantum point contact.

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.

基于0.15μm SOI工艺的耐高温短沟器件设计与实现

绝缘体上硅(Silicon on insulator,SOI)技术在200~400℃高温器件和集成电路方面有着广泛的应用前景,但对于沟道长度≤0.18μm的短沟道器件在200℃以上的高温下阈值电压漂移量达40%以上,漏电流达μA级,无法满足电路设计要求。本文研究了基于0.15μm SOI工艺的1.5 V MOS器件电特性在高温下的退化机理和抑制方法,通过增加栅氧厚度、降低阱浓度、调整轻掺杂漏离子注入工艺等优化方法,实现了一种性能良好的短沟道高温SOI CMOS器件,在25~250℃温度范围内,该器件阈值电压漂移量<30%,饱和电流漂移量<15%,漏电流<1 nA/μm。此外采用仿真的方法分析了器件在高温下的漏区电势和电场的变化规律,将栅诱导漏极泄漏电流效应与器件高温漏电流关联起来,从而定性地解释了SOI短沟道器件高温漏电流退化的机理。

大偏角短引渠侧向进水泵站流场流态优化

为了改善大偏角短引渠侧向进水泵站前池、进水池内偏流、回流和漩涡等不良流态,以某大型大偏角短引渠侧向进水泵站工程为研究对象,采用物理模型试验和数值模拟相结合的方式对初步设计方案下的前池、进水池流态进行分析,提出流速偏差系数λ作为评价指标,对工程进行优化,探讨前池的结构性改造对水流的整流效果,得出“弧形隔墩+改变底坡坡度+开设消涡孔”的组合方案为推荐整流方案,有效解决了前池及进水池内原设计存在的不良流态。研究结果表明,该整流方案使各个机组进水池偏差系数分别下降了37.03%、12.99%、22.29%、22.04%,显著改善了前池,进水池流态。研究结果可为类似大偏角短引渠侧向进水泵站前池及进水池流场流态优化提供参考,也可为类似短引渠泵站工程和进水建筑物的设计提供参考。

基于多通道卷积神经网络的柴油机复合故障诊断

针对复合故障诊断精度较低的问题,开展了柴油机多故障模拟实验,构建了基于AlexNet改进的多通道二维卷积神经网络模型,采用短时傅里叶变换将一维振动信号转换为二维时频图,导入构建的模型进行训练,实现特征自适应提取的故障诊断。将诊断结果与单通道卷积神经网络诊断结果比较发现:单通道卷积神经网络诊断只有在测点设置靠近故障源的情况下才能够获得较高的故障诊断准确率,否则诊断准确率明显降低,且复合故障诊断精度较低;多通道卷积神经网络的单故障和复合故障诊断精度均得到了提升,其中复合故障诊断精度提升了11.4%。

单侧双通道内镜治疗重度腰椎管狭窄症的近期疗效分析

目的探讨单侧双通道内镜治疗重度腰椎管狭窄症的近期疗效及对患者硬膜囊面积、功能恢复情况的影响。方法前瞻性选取2021年1月至2023年1月衢州市人民医院收治的重度腰椎管狭窄症患者60例为研究对象,采用随机数字表法分为观察组和对照组,各30例。观察组实施单侧双通道内镜技术,对照组实施传统腰椎后路椎板开窗减压术,比较两组患者手术效果、硬膜囊面积变化、功能恢复及并发症发生情况。结果观察组患者总优良率为93.33%,高于对照组的73.33%,差异有统计学意义(P<0.05)。与术前比较,术后1个月两组患者硬膜囊面积均增大,且观察组大于对照组,差异均有统计学意义(均P<0.05)。与术前比较,术后3个月两组患者日本骨科协会腰痛评分均升高,Oswestry功能障碍指数均降低,且观察组均上述指标均优于对照组,差异均有统计学意义(均P<0.05)。观察组和对照组并发症发生率分别为10.00%和20.00%,两组比较差异无统计学意义(P>0.05)。结论单侧双通道内镜治疗重度腰椎管狭窄症近期疗效显著,可明显减轻患者术后疼痛程度,改善患者腰椎功能。

基于购买漏斗模型的多渠道网络广告效应研究

从企业发起渠道(firm-initiated contacts,FICs)和客户发起渠道(customer-initiated contacts,CICs)两方面,探讨了不同网络广告的短期及长期效应。通过对网络广告短期效应和长期效应的综合测评,以期为企业营销合理分配广告预算提供实践指导。实证研究发现,从短期来看,FICs品牌型广告的即时效应最大,从长期来看,FICs广告有着最强的长期累积效应,特别是短信广告。FICs广告的效应持续时间比CICs广告的效应持续时间更长。CICs品牌型搜索广告在首页访问阶段产生了更高的效应,CICs通用型搜索广告在主页访问和详情页访问阶段的效应较为相近,而FICs广告能更有效地吸引客户转到特定的产品详情页面。

15 nm Bulk nFinFET器件性能研究及参数优化

为研究Bulk FinFET工作时基本结构参数、器件温度和栅极材料对其性能的影响,建立了一个15 nm n型Bulk FinFET器件模型,仿真分析了不同栅长、鳍宽、鳍高、沟道掺杂浓度、器件工作温度、栅极材料对器件性能的影响,发现增长栅长、降低鳍宽和增加鳍高有助于抑制短沟道效应;1×10^(17)cm^(-3)以下的低沟道掺杂浓度对器件特性影响不大,但高掺杂会使器件失效;器件工作温度的升高会导致器件性能的下降;采用高K介质材料作为栅极器件性能优于传统材料SiO_(2)。

基于交互式特征与多尺度特征的文本相似度研究

针对文本相似度分析过程中缺乏信息传递和忽略多元语义信息而导致相似度计算结果准确率低的问题,结合双向长短期记忆网络(BiLSTM),提出一种新颖的交互式特征与多尺度特征的文本相似度模型(IF-MSF)。首先,利用BiLSTM对句子进行编码提取全局特征矩阵,分别用软注意力机制和余弦相似度对特征矩阵进行交互,以相互传递两组特征矩阵内部的语义信息。其次,加权两组交互式特征以综合所有交互信息,并利用BiLSTM对加权交互式特征和初始编码特征再编码以捕获特征之间的差异信息。再次,使用多尺度卷积提取差异信息的多元语义特征并结合通道注意力机制增强重要特征信息。最后,融合两组增强特征判断文本对是否相似。实验选取2个数据集来验证该方法,该模型F1值分别取得最高值88.15%和85.03%,优于其他方法。

一种面向112 Gb/s PAM4接收机的自适应均衡设计方案

提出了一种适用于超短距离(Very Short Reach,VSR)信道、面向112 Gb/s PAM4(Pulse Amplitude Modulation 4)接收机的自适应均衡设计方案。在该方案中,接收机前端利用3个连续时间线性均衡器(Continuous Time Linear Equalizer,CTLE)对信号分别在高频、中频和低频进行补偿,可变增益放大器(Variable Gain Amplifier,VGA)和饱和放大器(Saturation Amplifier,SatAmp)则用于对信号幅值的缩放。除了3个数据采样器外,引入4个辅助采样器用于进一步改善阈值自适应算法性能。同时,采用符号最小均方算法,利用接收端数据采样器和辅助采样器之间的偏移推动辅助参考电压收敛到信号星座电平,从而确保PAM4接收信号的眼图在垂直方向上3个眼睛具有相等的间隔和恒定的信噪比(Signal-to-Noise Ratio,SNR)。仿真结果表明,所提出的112 Gb/s PAM4接收机能够在损耗为15 dB的信道上实现小于10~(-12)的误码率,并且具有良好的眼图性能,其最差眼高为75 mV,眼宽为0.34 UI(Unit Interval),与传统方案相比具有显著的性能提升。

生鲜农产品数字化超短链的渠道风险识别与治理机制

为了更好理解和发挥现代生鲜农产品数字化超短链的渠道优势,需要加强超短链的渠道风险识别与治理防控。基于供应链渠道风险及其治理问题,系统识别由直销和分销渠道组成的超短链渠道系统结构与业务风险因素,构建系统动力学模型,从时效、质量和数量风险角度探讨渠道系统核心业务的风险及其影响,得出相关治理机制。研究表明,超短链渠道系统具有典型的时间敏感性特征,当前阶段直销渠道抵抗质量风险的能力较分销渠道强,需要考虑渠道系统的辐射范围。研究结果深化了对生鲜农产品数字化超短链渠道风险内涵的认知,提供了超短链渠道系统安全、高效运营的路径和方法,对推动超短链渠道系统高质量的健康发展具有重要意义。

集成侧墙技术的80nm栅GaN HEMT

目前业界主要采用电子束曝光技术制作高频氮化镓高电子迁移率晶体管(GaN HEMT)的深亚微米T型栅,存在效率低下、良率不足和成本较高的问题。本文采用集成侧墙技术,在6英寸工业化产线上首次成功制造了纯光学曝光的80 nm T型栅GaN HEMT,并对器件性能参数进行了全面表征和分析。器件单位栅宽(每毫米)下,最大输出电流Id,max为993 mA,峰值跨导Gm,peak为385 mS;阈值电压Uth为-3.25 V,关态击穿电压超过80 V;电流增益截止频率(fT)和功率增益截止频率(fmax)分别为64 GHz和175 GHz。在28 V工作时,器件在16 GHz下的饱和输出功率、功率增益和功率附加效率分别为26.95 dBm(每毫米4.9 W)、11.08 dB和49.78%;在30 GHz下器件的饱和输出功率、功率增益和功率附加效率分别为26.15 dBm(每毫米4.1 W)、8.8 dB和44%。结果表明,集成侧墙技术在深亚微米GaN HEMT制造中具备较好的应用前景。

渐变沟道全耗尽SOI MOSFET漏致势垒降低效应研究

目的 集SOI MOSFET(绝缘衬底上的硅金属氧化物半导体场效应晶体管)器件结构与渐变沟道的优点于一体,提出渐变沟道全耗尽SOI MOSFET器件结构,以提高MOSFET器件的微观物理性能。方法 分别列出沟道不同掺杂浓度的2个区域的泊松方程并求解,建立阈值电压模型。依据计算结果,详细分析沟道高掺杂区的掺杂浓度和掺杂长度、栅氧化层的介电常数、硅膜厚度等物理参数对漏致势垒降低(DIBL)效应的影响。结果 DIBL随沟道高掺杂区的掺杂浓度的增大而变小,随掺杂长度的减小而变小,随栅氧化层的介电常数的增大而变小,随硅层厚度减薄而变小。结论 渐变掺杂沟道结构能够有效抑制器件的DIBL。该研究结果不仅对器件的理论研究有一定的意义,而且对器件的设计提供了一定的参考价值。