An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain (DMG-LDD) metal-oxide-semiconductor field-effect transistor (MOSFET) is presented...An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain (DMG-LDD) metal-oxide-semiconductor field-effect transistor (MOSFET) is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects (SCEs) and the drain induced barrier lowering (DIBL) more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.展开更多
In the present work, a two-dimensional(2D) analytical framework of triple material symmetrical gate stack(TMGS)DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along wit...In the present work, a two-dimensional(2D) analytical framework of triple material symmetrical gate stack(TMGS)DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.展开更多
N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 6...N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.展开更多
Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have bee...Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.展开更多
A novel shorted anode lateral-insulated gate bipolar transistor(SA LIGBT)with snapback-free characteristic is proposed and investigated.The device features a controlled barrier V_(barrier)and resistance R_(SA)in anode...A novel shorted anode lateral-insulated gate bipolar transistor(SA LIGBT)with snapback-free characteristic is proposed and investigated.The device features a controlled barrier V_(barrier)and resistance R_(SA)in anode,named CBR LIGBT.The electron barrier is formed by the P-float/N-buffer junction,while the anode resistance includes the polysilicon layer and N-float.At forward conduction stage,the V_(barrier)and R_(SA)can be increased by adjusting the doping of the P-float and polysilicon layer,respectively,which can suppress the unipolar mode to eliminate the snapback.At turn-off stage,the low-resistance extraction path(N-buffer/P-float/polysilicon layer/N-float)can quickly extract the electrons in the N-drift,which can effectively accelerate the turn-off speed of the device.The simulation results show that at the same V_(on) of 1.3 V,the E_(off)of the CBR LIGBT is reduced by 85%,73%,and 59.6%compared with the SSA LIGBT,conventional LIGBT,and TSA LIGBT,respectively.Additionally,at the same Eoffof 1.5 m J/cm^(2),the CBR LIGBT achieves the lowest V_(on) of 1.1 V compared with the other LIGBTs.展开更多
This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potenti...This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.展开更多
We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overl...We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson's equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.展开更多
为了提高光伏发电功率预测精度,提出了一种基于长短期时序数据融合的Transformer生成式预测模型:LSTformer,能准确有效地预测光伏发电功率。LSTformer创新性地提出了时序分析模块(time series analysis,TSA)、时序特征融合模块(time ser...为了提高光伏发电功率预测精度,提出了一种基于长短期时序数据融合的Transformer生成式预测模型:LSTformer,能准确有效地预测光伏发电功率。LSTformer创新性地提出了时序分析模块(time series analysis,TSA)、时序特征融合模块(time series feature fusion,TSFF)和多周期嵌入模块(cycleEmbed),利用数据融合解决难以提取多时间尺度时序特征问题。设计时间卷积前馈(time convolution feedforward,TCNforward)单元,在编解码的过程中进一步提取时序特征。利用某光伏电站实际历史发电数据,通过实验验证LSTformer模型在光伏发电功率预测领域得到最低的均方误差(mean squared error,MSE)、平均绝对误差(mean absolute error,MAE),并通过消融实验验证了各模块的有效性。展开更多
文摘An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain (DMG-LDD) metal-oxide-semiconductor field-effect transistor (MOSFET) is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects (SCEs) and the drain induced barrier lowering (DIBL) more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.
文摘In the present work, a two-dimensional(2D) analytical framework of triple material symmetrical gate stack(TMGS)DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.
基金This study was jointly funded by the National Key R&D Program of China[grant number 2022YFC3004103]the National Natural Foundation of China[grant number 42275003]+2 种基金the Beijing Science and Technology Program[grant number Z221100005222012]the Beijing Meteorological Service Science and Technology Program[grant number BMBKJ202302004]the China Meteorological Administration Youth Innovation Team[grant number CMA2023QN10].
基金Project supported by the National Natural Science Foundation of China (Grant No 60376024).
文摘N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60976068 and 60936005)Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 708083),Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 200807010010)
文摘Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61604027 and 61704016)the Fund from Chongqing Technology Innovation and Application Development(Key Industry Research and Development),China(Grant No.cstc2018jszx-cyzd0646)。
文摘A novel shorted anode lateral-insulated gate bipolar transistor(SA LIGBT)with snapback-free characteristic is proposed and investigated.The device features a controlled barrier V_(barrier)and resistance R_(SA)in anode,named CBR LIGBT.The electron barrier is formed by the P-float/N-buffer junction,while the anode resistance includes the polysilicon layer and N-float.At forward conduction stage,the V_(barrier)and R_(SA)can be increased by adjusting the doping of the P-float and polysilicon layer,respectively,which can suppress the unipolar mode to eliminate the snapback.At turn-off stage,the low-resistance extraction path(N-buffer/P-float/polysilicon layer/N-float)can quickly extract the electrons in the N-drift,which can effectively accelerate the turn-off speed of the device.The simulation results show that at the same V_(on) of 1.3 V,the E_(off)of the CBR LIGBT is reduced by 85%,73%,and 59.6%compared with the SSA LIGBT,conventional LIGBT,and TSA LIGBT,respectively.Additionally,at the same Eoffof 1.5 m J/cm^(2),the CBR LIGBT achieves the lowest V_(on) of 1.1 V compared with the other LIGBTs.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60976068and60936005)the Cultivation Fund of the Major Science and Technology Innovation,Ministry of Education,China(Grant No.708083)+1 种基金Specialized Research Fund for the Doctoral Program of Higher Education(Grant No.200807010010)the Fundamental Research Funds for the Central Universities
文摘This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China(Grant No.708083)the Fundamental Research Funds for the Central Universities of China(Grant No.20110203110012)
文摘We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson's equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.