A limiting amplifier IC implemented in 65 nm CMOS technology and intended for high-speed optical fiber communications is described in this paper.The inductorless limiting amplifier incorporates5-stage 8 dB gain limiti...A limiting amplifier IC implemented in 65 nm CMOS technology and intended for high-speed optical fiber communications is described in this paper.The inductorless limiting amplifier incorporates5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance,a high speed output buffer with novel third order active feedback,and a high speed full-wave rectifier.The receiver signal strength indictor(RSSI) can detect input signal power with 33 dB dynamic range,and the limiting amplifier features a programmable loss of signal(LOS) indication with external resistor.The sensitivity of the limiting amplifier is 5.5mV at BER = 10 ^(-12) and the layout area is only 0.53 ×0.72 mm because of no passive inductor.The total gain is over 41 dB,and bandwidth exceeds12 GHz with 56 mW power dissipation.展开更多
设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 m Vpp的差分电压信号。该全差分前置放大电路采用0.18μm CMOS工艺进...设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 m Vpp的差分电压信号。该全差分前置放大电路采用0.18μm CMOS工艺进行设计,当光电二极管电容为250 f F时,该光接收机前置放大电路的跨阻增益为92 d BΩ,-3 d B带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 p A/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 m W,限幅放大器功耗为80 m W,输出缓冲器功耗为40 m W,其芯片面积为800μm×1 700μm。展开更多
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA010301)the National Natural Science Foundation of China(No.60976029)
文摘A limiting amplifier IC implemented in 65 nm CMOS technology and intended for high-speed optical fiber communications is described in this paper.The inductorless limiting amplifier incorporates5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance,a high speed output buffer with novel third order active feedback,and a high speed full-wave rectifier.The receiver signal strength indictor(RSSI) can detect input signal power with 33 dB dynamic range,and the limiting amplifier features a programmable loss of signal(LOS) indication with external resistor.The sensitivity of the limiting amplifier is 5.5mV at BER = 10 ^(-12) and the layout area is only 0.53 ×0.72 mm because of no passive inductor.The total gain is over 41 dB,and bandwidth exceeds12 GHz with 56 mW power dissipation.
文摘设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 m Vpp的差分电压信号。该全差分前置放大电路采用0.18μm CMOS工艺进行设计,当光电二极管电容为250 f F时,该光接收机前置放大电路的跨阻增益为92 d BΩ,-3 d B带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 p A/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 m W,限幅放大器功耗为80 m W,输出缓冲器功耗为40 m W,其芯片面积为800μm×1 700μm。
