This paper introduces a design of high-precision high-voltage fiber-optic analog sig-nal isolation converter based on the technology of Voltage-to-Frequency (V/F) and Frequency-to-Voltage (F/V) conversion. It describe...This paper introduces a design of high-precision high-voltage fiber-optic analog sig-nal isolation converter based on the technology of Voltage-to-Frequency (V/F) and Frequency-to-Voltage (F/V) conversion. It describes the principle, system configuration and hardware design.展开更多
We develop an improved design of thin gap chamber （TGC） simulation signal source. To further simulate the feature of TGC detector, a novel thought is proposed. The TGC source has 256 channels. Every channel can rand...We develop an improved design of thin gap chamber （TGC） simulation signal source. To further simulate the feature of TGC detector, a novel thought is proposed. The TGC source has 256 channels. Every channel can randomly output the signal in 25 ns. The design is based on true random number generator （TRNG）. Considering the electrical connection between the TGC source and the developing trigger electronics, the GFZ connector is used. The experimental results show that the improved TGC simulation signal source can uniformly output the random signal in every channel. The output noise is less than 3 mVrms.展开更多
A state machine can make program designing quicker,simpler and more efficient. This paper describes in detail the model for a state machine and the idea for its designing and gives the design process of the state mach...A state machine can make program designing quicker,simpler and more efficient. This paper describes in detail the model for a state machine and the idea for its designing and gives the design process of the state machine through an example of audio signal generator system based on Labview. The result shows that the introduction of the state machine can make complex design processes more clear and the revision of programs easier.展开更多
The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and a...The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.展开更多
Most acceleration diagrams show high levels of unpredictability, as a result, it is the best to avoid using diagrams of earthquake acceleration spect~＇a, even if the diagrams recorded at the site in question. In orde...Most acceleration diagrams show high levels of unpredictability, as a result, it is the best to avoid using diagrams of earthquake acceleration spect~＇a, even if the diagrams recorded at the site in question. In order to design earthquake resistant structures, we, instead, suggest constructing a design spectrum using a set of spectra that have common characteristics to the recorded acceleration diagrams at a particular site and smoothing the associated data. In this study, we conducted a time history analysis and determined a design spectrum for the region near the Lali tunnel in Southwestern Iran. We selected 13 specific ground motion records from the rock site to construct the design spectrum. To process the data, we first applied a base-line correction and then calculated the signal-to-noise ratio （]~SN） for each record. Next, we calculated the Fourier amplitude spectra of the acceleration pertaining to the signal window （1）, and the Fourier amplitude spectra of the associated noise （2）. After dividing each spectra by the square root of the selected window interval, they were divided by each other （1 divided by 2）, in order to obtain the ~SN ratio （filtering was also applied）. In addition, all data were normalized to the peak ground acceleration （PGA）. Next, the normalized vertical and horizontal responses and mean response spectrum （50%） and the mean plus-one standard deviation （84%） were calculated for all the selected ground motion records at 5% damping. Finally, the mean design spectrum and the mean plus-one standard deviation were plotted for the spectrums. The equation of the mean and the above-mean design spectrum at the Lali tunnel site are also provided, along with our observed conclusions.展开更多
Under the condition of asymmetric information,the Spence 's Job Market Signaling Model is generally applied to inspect the design capability of a designer and his labor and efforts to be invested; however,since th...Under the condition of asymmetric information,the Spence 's Job Market Signaling Model is generally applied to inspect the design capability of a designer and his labor and efforts to be invested; however,since the"prior probability"and "posterior probability"have great uncertainties,the practical effect of this model is poor. On the basis of analyzing reverse selection questions,this paper provides a design capability screening model,which can make a designer automatically expose his hidden information so that necessary actions can be taken as required by the owner to realize risk sharing. A calculation example is finally given to demonstrate that the new model is helpful for an owner to select a designer with high professional level and to lead the designer to work hard,so it is of significant application value.展开更多
A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very la...A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.展开更多
Under the direction of design space theory,in this paper we discuss the design of a superscalar pipelining using the way of multiple issues,and the implement of a superscalar based RISC DSP architecture,SDSP.Furthermo...Under the direction of design space theory,in this paper we discuss the design of a superscalar pipelining using the way of multiple issues,and the implement of a superscalar based RISC DSP architecture,SDSP.Furthermore,in this paper we discuss the validity of instruction prefetch,the branch prediction,the depth of instruction window and other issues that can affect the performance of superscalar DSP.展开更多
基金This work was supported by the National Meg-Science Engineering Project of the Chinese Government.
文摘This paper introduces a design of high-precision high-voltage fiber-optic analog sig-nal isolation converter based on the technology of Voltage-to-Frequency (V/F) and Frequency-to-Voltage (F/V) conversion. It describes the principle, system configuration and hardware design.
基金Supported by the State Key Laboratory of Particle Detection and Electronicsthe National Natural Science Foundation of China under Grant No 11375179
文摘We develop an improved design of thin gap chamber （TGC） simulation signal source. To further simulate the feature of TGC detector, a novel thought is proposed. The TGC source has 256 channels. Every channel can randomly output the signal in 25 ns. The design is based on true random number generator （TRNG）. Considering the electrical connection between the TGC source and the developing trigger electronics, the GFZ connector is used. The experimental results show that the improved TGC simulation signal source can uniformly output the random signal in every channel. The output noise is less than 3 mVrms.
文摘A state machine can make program designing quicker,simpler and more efficient. This paper describes in detail the model for a state machine and the idea for its designing and gives the design process of the state machine through an example of audio signal generator system based on Labview. The result shows that the introduction of the state machine can make complex design processes more clear and the revision of programs easier.
基金Supported by National Natural Science Foundation of Zhejiang Province
文摘The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.
文摘Most acceleration diagrams show high levels of unpredictability, as a result, it is the best to avoid using diagrams of earthquake acceleration spect~＇a, even if the diagrams recorded at the site in question. In order to design earthquake resistant structures, we, instead, suggest constructing a design spectrum using a set of spectra that have common characteristics to the recorded acceleration diagrams at a particular site and smoothing the associated data. In this study, we conducted a time history analysis and determined a design spectrum for the region near the Lali tunnel in Southwestern Iran. We selected 13 specific ground motion records from the rock site to construct the design spectrum. To process the data, we first applied a base-line correction and then calculated the signal-to-noise ratio （]~SN） for each record. Next, we calculated the Fourier amplitude spectra of the acceleration pertaining to the signal window （1）, and the Fourier amplitude spectra of the associated noise （2）. After dividing each spectra by the square root of the selected window interval, they were divided by each other （1 divided by 2）, in order to obtain the ~SN ratio （filtering was also applied）. In addition, all data were normalized to the peak ground acceleration （PGA）. Next, the normalized vertical and horizontal responses and mean response spectrum （50%） and the mean plus-one standard deviation （84%） were calculated for all the selected ground motion records at 5% damping. Finally, the mean design spectrum and the mean plus-one standard deviation were plotted for the spectrums. The equation of the mean and the above-mean design spectrum at the Lali tunnel site are also provided, along with our observed conclusions.
基金Sponsored by State Key Laboratory of Subtropical Building Science,Autonomous Research Topics(Grant No.x2tjc7100870)
文摘Under the condition of asymmetric information,the Spence 's Job Market Signaling Model is generally applied to inspect the design capability of a designer and his labor and efforts to be invested; however,since the"prior probability"and "posterior probability"have great uncertainties,the practical effect of this model is poor. On the basis of analyzing reverse selection questions,this paper provides a design capability screening model,which can make a designer automatically expose his hidden information so that necessary actions can be taken as required by the owner to realize risk sharing. A calculation example is finally given to demonstrate that the new model is helpful for an owner to select a designer with high professional level and to lead the designer to work hard,so it is of significant application value.
基金supported by the National Natural Science Foundation of China under Grant No.90407007University Science Foundation of China under Grant No R0820207
文摘A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.
文摘Under the direction of design space theory,in this paper we discuss the design of a superscalar pipelining using the way of multiple issues,and the implement of a superscalar based RISC DSP architecture,SDSP.Furthermore,in this paper we discuss the validity of instruction prefetch,the branch prediction,the depth of instruction window and other issues that can affect the performance of superscalar DSP.
