Effects of gate-buffer combined with a p-type spacer structure on silicon carbide metal semiconductor field-effect transistors

An improved structure of silicon carbide metal-semiconductor field-effect transistors （MESFET） is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.

New 4H silicon carbide metal semiconductor field-effect transistor with a buffer layer between the gate and the channel layer

A new 4H silicon carbide metal semiconductor field-effect transistor （4H-SiC MESFET） structure with a buffer layer between the gate and the channel layer is proposed in this paper for high power microwave applications. The physics-based analytical models for calculating the performance of the proposed device are obtained by solving one- and two-dimensional Poisson＇s equations. In the models, we take into account not only two regions under the gate but also a third high field region between the gate and the drain which is usually omitted. The direct-current and the alternating- current performances for the proposed 4H-SiC MESFET with a buffer layer of 0.2 ~tm are calculated. The calculated results are in good agreement with the experimental data. The current is larger than that of the conventional structure. The cutoff frequency （fT） and the maximum oscillation frequency （fmax） are 20.4 GHz and 101.6 GHz, respectively, which are higher than 7.8 GHz and 45.3 GHz of the conventional structure. Therefore, the proposed 4H-SiC MESFET structure has better power and microwave performances than the conventional structure.

适用于SiC MOSFET的漏源电压积分自适应快速短路保护电路研究

SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。

SiC MOSFET开关瞬态解析建模综述

在评估和优化半导体器件开关瞬态特性领域,解析模型因具有简单、直观、应用便捷等优点得到广泛研究。相较同等功率等级的硅基功率器件,碳化硅(silicon carbide,SiC)金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)可以应用于更高开关速度,其开关瞬态特性更为复杂,开关瞬态解析建模也更加困难。该文总结现有的针对SiC MOSFET与二极管换流对的开关瞬态解析建模方法,在建模过程中依次引入各种简化假设,按照简化程度由低到高的顺序,梳理解析建模的逐步简化过程。通过对比,评估各模型的优缺点以及适用场合,对其中准确性、实用性都较强的分段线性模型进行详细介绍;之后,对开关瞬态建模中关键参数的建模方法进行总结与评价;最后,指出现有SiC MOSFET开关瞬态解析模型中存在的问题,并对其未来发展给出建议。

SiC MOSFET高温栅氧可靠性研究

碳化硅SiC(silicon carbide)具有优良的电学和热学特性,是一种前景广阔的宽禁带半导体材料。SiC材料制成的功率MOSFET(metal-oxide-semiconductor field-effect transistor)非常适合应用于大功率领域,而高温栅氧可靠性是大功率MOSFET最需要关注的特性之一。通过正压高温栅偏试验和负压高温栅偏试验对比了自研SiC MOSFET和国外同规格SiC MOSFET的高温栅氧可靠性。负压高温栅偏试验结果显示自研SiC MOSFET与国外SiC MOSFET的阈值电压偏移量基本相等,阈值电压偏移量百分比最大相差在4.52%左右。正压高温栅偏试验的结果显示自研SiC MOSFET的阈值电压偏移量较小,与国外SiC MOSFET相比,自研SiC MOSFET的阈值电压偏移量百分比最大相差11%。自研器件占优势的原因是在SiC/SiO2界面处引入了适量的氮元素,钝化界面缺陷的同时,减少了快界面态的产生,使总的界面态密度被降到最低。

SiC MOSFET驱动特性及器件国产化后的影响分析

碳化硅金属氧化物半导体场效应晶体管SiC MOSFET(silicon carbide metal-oxide-semiconductor field-effect transistor)作为一种新型、广泛应用的开关器件,在实际应用中具有更快的开关速度和更低的器件损耗,可以提高变换器的效率,体现更好的性能。针对SiC MOSFET驱动特性,分析寄生参数对其的影响;搭建双脉冲实验平台,分析栅源电压与SiC MOSFET导通时间的关系;针对现有国产SiC MOSFET存在的不足之处,基于搭建的实验平台及其他电源产品,对SiC MOSFET进行国产化器件替代后导通时间、驱动损耗及负压幅值变化的相关分析。

动态高温反偏应力下的SiC MOSFET测试平台及其退化机理研究

为研究SiC MOSFET在动态漏源应力下的退化机理,开发了一种具有dVds/dt可调功能、最高可达80 V/ns的动态反向偏置测试平台。针对商用SiC MOSFET进行动态高温反偏实验,讨论高电压变化率的动态漏源应力对SiC MOSFET电学特性的影响。实验结果显示,器件的阈值电压和体二极管正向导通电压增加,说明器件JFET区上方的栅氧层和体二极管可能发生了退化。通过Sentaurus TCAD分析了在高漏源电压及高电压变化率下平面栅型SiC MOSFET的薄弱位置,在栅氧层交界处和体二极管区域设置了空穴陷阱,模拟动态高温反偏对SiC MOSFET动静态参数的影响。

SiC MOSFET器件栅氧可靠性研究综述

碳化硅金属氧化物半导体场效应晶体管SiC MOSFET(silicon carbide metal-oxide-semiconductor field effect transistor)因具有高压、高频、低导通损耗等优异特性而获得产业界广泛关注,但相比于硅基IGBT,SiC/SiO_(2)栅氧界面高缺陷密度引起的栅氧可靠性问题成为制约SiC MOSFET器件规模化应用的关键瓶颈。通过对近年来国内外SiC MOSFET栅氧可靠性研究成果的梳理和分析,阐述了当前栅氧可靠性问题的形成原因,归纳总结了各类常用的栅氧可靠性评估方法,并进行了比较分析,最后重点探讨了极端工况下SiC MOSFET栅氧可靠性及其提升技术的发展现状。

SiC MOSFET的质子单粒子效应

SiC金属氧化物半导体场效应晶体管(MOSFET)在深空探测领域具有广阔的应用前景,但空间质子引发的单粒子效应(SEE)对航天器稳定运行造成了严重威胁。对平面栅结构与非对称沟槽栅结构的SiC MOSFET进行了能量为70、100与200 MeV的质子辐照实验。实验结果表明,两种SiC MOSFET的单粒子烧毁(SEB)阈值电压均大于额定漏源电压的75%;SEB阈值电压随质子能量升高而降低。对两种器件进行辐照后栅应力测试发现,两种结构的器件由于沟道不同而对栅应力的响应存在差异;不同的质子能量会在栅极引入不同程度的辐射损伤,低能质子更容易在栅氧化层发生碰撞而引入氧化物潜在损伤。该研究可为揭示SiC MOSFET质子SEE机理和评估抗辐射能力提供参考。

基于有源箝位技术的SiC MOSFET串联均压有源驱动电路研究

功率器件串联技术是实现高压应用的有效途径之一,而串联应用的主要制约因素是串联器件之间的动态均压问题。该文针对不均压条件下串联器件的关断行为进行了理论分析,探究不均压的产生机理,提出一种基于有源箝位技术的碳化硅金属-氧化物半导体场效应晶体管串联均压有源驱动,其利用有源箝位电路检测串联器件之间的电压不均衡,并箝位电压尖峰,通过反馈控制器件栅极电荷及开关瞬态行为实现均压。该方案不存在不均压的调节周期,即使在交变负载下依然能在每一个开关周期的关断时间内实现均压控制。此外,该文还详细介绍所提出方案的电路原理和参数设计过程,并通过试验验证该方案均压控制效果的有效性。结果表明,所提出方案具有有源箝位电路拓展性强的特点;是独立于原有栅极驱动电路的辅助电路,适用性强;且控制电路结构简单,无需可编程逻辑芯片和额外的信号隔离。

基于栅极参考电压的SiC MOSFET栅极氧化物健康状态在线监测方法

栅极氧化物退化是限制SiC MOSFET进一步广泛应用的关键可靠性问题。在线监测能够实时获取栅极氧化物健康状态,是提升SiC MOSFET可靠性的重要手段,因此提出一种基于栅极参考电压的SiC MOSFET栅极氧化物健康状态在线监测方法,并详细介绍了利用栅极参考电压监测栅极氧化物健康状态的基本原理;提出一种栅极参考电压在线提取电路,经脉冲测试验证可以实现在线提取,经老化试验验证可以有效监测栅极氧化物健康状态。所提电路可以集成在栅极驱动中,不会显著增加系统复杂程度。

一种改进型抑制SiC MOSFET桥臂串扰的门极驱动设计

针对传统驱动中SiC MOSFET在高开关频率下其寄生参数造成的桥臂串扰更加严重,而现有抑制串扰驱动电路多以增加开关损耗、增长开关延时和增加控制复杂度为代价的问题,根据降低串扰产生过程中驱动回路阻抗的思路,提出1种在栅源极间增加PNP三极管串联二极管和电容的新型有源米勒钳位门极驱动设计,分析其工作原理,并对改进驱动电路并联电容参数进行计算设计;搭建直流母线电压为300 V的同步Buck变换器双脉冲测试实验平台,分别与传统串扰抑制电路、典型串扰抑制电路的正负向串扰电压尖峰抑制效果和开通关断速度进行对比分析。实验结果表明,所提串扰抑制驱动电路正负向电压尖峰分别比传统和典型串扰抑制电路降低了80%和40%,同时减少了32%的器件开关延时。

Fabrication and Characterization of 1700 V 4H-SiC Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.

Design consideration and fabrication of 1.2-kV 4H-SiC trenched-and-implanted vertical junction field-effect transistors

We present the design consideration and fabrication of 4H-SiC trenched-and-implanted vertical junction field-effect transistors （TI-VJFETs）. Different design factors, including channel width, channel doping, and mesa height, are con- sidered and evaluated by numerical simulations. Based on the simulation result, normally-on and normally-off devices are fabricated. The fabricated device has a 12 μm thick drift layer with 8 × 10^15 cm^-3 N-type doping and 2.6 μm channel length. The normally-on device shows a 1.2 kV blocking capability with a minimum on-state resistance of 2.33 mΩ.cm2, while the normally-off device shows an on-state resistance of 3.85 mΩ.cm2. Both the on-state and the blocking performances of the device are close to the state-of-the-art values in this voltage range.

基于PZT压电陶瓷的SiC MOSFET缓冲吸收电路

在高速关断过程中,碳化硅(silicon carbide,SiC)金属-氧化物半导体场效应晶体管器件呈现出严重的电压过冲和振荡,降低器件电压裕量。通常,采用缓冲吸收电路改善SiC器件的关断电压轨迹。然而,现有研究忽略SiC器件与吸收电路的交互规律和工作温度对吸收电路性能的影响,限制缓冲吸收电路的应用。针对这些问题,该文提出一种基于锆钛酸铅(lead zirconate titanate,PZT)压电陶瓷的缓冲吸收电路,分析PZT的温度特性,通过建立半桥电路与PZT缓冲吸收电路的高精度交互模型,揭示PZT缓冲吸收电路与SiC器件的耦合规律,利用特征方程-根轨迹方法,定量刻画PZT缓冲吸收电路的参数设计域。对比评估工作温度对多种缓冲吸收电路性能的影响。实验结果表明,所提设计方法能很好地抑制关断电压过冲与振荡,验证设计方法的有效性。相较于传统RC缓冲吸收电路,PZT缓冲吸收电路在工作温度发生变动后,仍然具有很好的抑制效果,且抑制效果随工作温度的上升而不断增强。为SiC功率器件的暂态稳定性分析,以及功率模块和缓冲吸收电路的集成设计,提供有益的参考。

用于SiC MOSFET开关电压测量的非接触式电场耦合电压传感器

准确测量碳化硅(silicon carbide,SiC)金属–氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)开关电压是评估SiC MOSFET开关特性、计算开关损耗、优化变换器设计的关键。随着SiC MOSFET开关速度、耐压及功率密度的提升,开关电压测量难的问题逐渐凸显,因此对电压传感器的带宽、耐压和侵入性提出了新的要求。该文以SiC MOSFET的开关电压为研究对象,根据目前开关电压的测量需求,提出一种利用电场耦合原理测量开关电压的非接触式电压传感器,并设计混合积分电路对传感器输出信号进行电压重构。在此基础上,通过仿真和计算着重分析电场耦合电压传感器的结构和电路参数的设计依据。传感器带宽范围为5Hz~260MHz,量程为-1000~+1000V,输入电容约为0.73pF,最后利用双脉冲测试,将其与商用示波器探头的测量结果进行对比,验证电场耦合电压传感器的准确性。

Experiment and simulation on degradation and burnout mechanisms of SiC MOSFET under heavy ion irradiation

Experiments and simulation studies on 283 MeV I ion induced single event effects of silicon carbide(SiC) metal–oxide–semiconductor field-effect transistors(MOSFETs) were carried out. When the cumulative irradiation fluence of the SiC MOSFET reached 5×10^(6)ion·cm^(-2), the drain–gate channel current increased under 200 V drain voltage, the drain–gate channel current and the drain–source channel current increased under 350 V drain voltage. The device occurred single event burnout under 800 V drain voltage, resulting in a complete loss of breakdown voltage. Combined with emission microscope, scanning electron microscope and focused ion beam analysis, the device with increased drain–gate channel current and drain–source channel current was found to have drain–gate channel current leakage point and local source metal melt, and the device with single event burnout was found to have local melting of its gate, source, epitaxial layer and substrate. Combining with Monte Carlo simulation and TCAD electrothermal simulation, it was found that the initial area of single event burnout might occur at the source–gate corner or the substrate–epitaxial interface, electric field and current density both affected the lattice temperature peak. The excessive lattice temperature during the irradiation process appeared at the local source contact, which led to the drain–source channel damage. And the excessive electric field appeared in the gate oxide layer, resulting in drain–gate channel damage.

Proton induced radiation effect of SiC MOSFET under different bias

Radiation effects of silicon carbide metal–oxide–semiconductor field-effect transistors(SiC MOSFETs)induced by 20 MeV proton under drain bias(V_(D)=800 V,V_(G)=0 V),gate bias(V_(D)=0 V,V_(G)=10 V),turn-on bias(V_(D)=0.5 V,V_(G)=4 V)and static bias(V_(D)=0 V,V_(G)=0 V)are investigated.The drain current of SiC MOSFET under turn-on bias increases linearly with the increase of proton fluence during the proton irradiation.When the cumulative proton fluence reaches 2×10^(11)p·cm^(-2),the threshold voltage of SiC MOSFETs with four bias conditions shifts to the left,and the degradation of electrical characteristics of SiC MOSFETs with gate bias is the most serious.In the deep level transient spectrum test,it is found that the defect energy level of SiC MOSFET is mainly the ON2(E_(c)-1.1 eV)defect center,and the defect concentration and defect capture cross section of SiC MOSFET with proton radiation under gate bias increase most.By comparing the degradation of SiC MOSFET under proton cumulative irradiation,equivalent 1 MeV neutron irradiation and gamma irradiation,and combining with the defect change of SiC MOSFET under gamma irradiation and the non-ionizing energy loss induced by equivalent 1 MeV neutron in SiC MOSFET,the degradation of SiC MOSFET induced by proton is mainly caused by ionizing radiation damage.The results of TCAD analysis show that the ionizing radiation damage of SiC MOSFET is affected by the intensity and direction of the electric field in the oxide layer and epitaxial layer.

桥式电路中SiC MOSFET串扰峰值预测算法研究

文中针对串扰电压峰值与驱动回路阻抗间的非线性关系,分段分析共源电感存在时串扰产生机理,提出一种碳化硅(silicon carbide,SiC)金属氧化物半导体场效应管(metal-oxide-semiconductor field-effect transistor,MOSFET)串扰电压的分析模型及预测算法。所提算法综合考虑共源电感、非线性极间电容等寄生参数与探头接线的影响,可实现引脚测量串扰电压的准确计算及器件内部串扰电压的提取。进一步,该算法针对栅极回路建模,并利用实测数据引入漏源电压与源极电流时变性,可适用于多桥臂电路及不同器件工况。最后,实验结果表明,所提算法可精准预测不同关断态驱动阻抗下的串扰峰值,其正向峰值平均预测误差仅为3.2%。该算法可为SiC MOSFET驱动电路设计提供定量计算参考。

Low working loss Si/4H-SiC heterojunction MOSFET with analysis of the gate-controlled tunneling effect

A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.