THE GROWTH OF MONOCRYSTALLINE SILICON THIN FILM ON INSULATOR (SOI) BY SCANNING ELECTRON BEAM

An experiment for preparation of SOI films by using the scanning electron beam to modify the polycrystalline silicon on SiO2 is presented. This method takes on the epitaxial lateral growth of liquid phase with the crystallon to form monocrystalline silicon films. The effects of the beam power density, scanning velocity, temperature of the substrates and the construction of samples on the quality of the monocrystalline silicon films were discussed. A good experimental result has been obtained, the monocrystalline silicon zone is nearly 200×25μm2.

Drain and Source on Insulator MOSFETs Fabricated by Local SIMOX Technology

To overcome the floating-body effect and self-heating effect of SOI devices,the drain and source on insulator (DSOI) structure is fabricated and tested.The low dose developed recently and low energy local SIMOX technology combined with the conventional CMOS technology is used to fabricate this kind of devices.Using this method,DSOI,SOI,and bulk MOSFETs are successfully integrated on a single chip.Test results show that the drain induced barrier lowering effect is suppressed.The breakdown voltage drain-to-source is greatly increased for DSOI devices due to the elimination of the floating-body effect.And the self-heating effect is also reduced and thus the reliability increased.At the same time,the advantage of SOI devices in speed is maintained.The technology makes it possible to integrate low voltage,low power,low speed SOI devices or high voltage,high power,high speed DSOI devices on one chip and it offers option for developing system-on-chip technology.

SOI高压LDMOS器件氧化层抗总电离剂量辐射效应研究

绝缘体上硅(SOI)高压横向扩散金属氧化物半导体(LDMOS)器件是高压集成电路的核心器件,对其进行了总电离剂量(TID)辐射效应研究。利用仿真软件研究了器件栅氧化层、场氧化层和埋氧化层辐射陷阱电荷对电场和载流子分布的调制作用,栅氧化层辐射陷阱电荷主要作用于器件沟道区,而场氧化层和埋氧化层辐射陷阱电荷则主要作用于器件漂移区;辐射陷阱电荷在器件内部感生出的镜像电荷改变了器件原有的电场和载流子分布,从而导致器件阈值电压、击穿电压和导通电阻等参数的退化。对80 V SOI高压LDMOS器件进行了总电离剂量辐射实验,结果表明在ON态和OFF态下随着辐射剂量的增加器件性能逐步衰退,当累积辐射剂量为200 krad(Si)时,器件的击穿电压大于80 V,阈值电压漂移为0.3 V,器件抗总电离剂量辐射能力大于200 krad(Si)。

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional（2D） Poisson＇s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage（BV） is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer（Q_（ntop）） is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

SDB-SOI制备过程中工艺控制

SOI(Silicom-On-Insulator)晶圆是绝缘氧化物上有一层薄硅膜的硅晶圆。在SDB-SOI晶圆制备过程中,需要在进行晶圆键合、磨削、抛光等工序过程中,通过对键合空腔、顶硅厚度、顶硅TTV、顶硅形状、顶硅表面等参数的控制,可以降低后续工序加工难度,最终制备出高质量的产品。

Effects of total dose irradiation on the threshold voltage of H-gate SOI NMOS devices

This work researched the impact of total dose irradiation on the threshold voltage of N-type metal oxide semiconductor field effect transistors(nMOSFETs) in silicon-on-insulator(SOI) technology.Using the subthreshold separation technology,the factor causing the threshold voltage shift was divided into two parts:trapped oxide charges and interface states,the effects of which are presented under irradiation.Furthermore,by analyzing the data,the threshold voltage shows a negative shift at first and then turns to positive shift when irradiation dose is lower.Additionally,the influence of the dose rate effects on threshold voltage is discussed.The research results show that the threshold voltage shift is more significant in low dose rate conditions,even for a low dose of100 krad(Si).The degeneration value of threshold voltage is 23.4%and 58.0%for the front-gate and the back-gate at the low dose rate,respectively.

FABRICATION AND TEST OF AN ELECTROMAGNETIC VIBRATING RING GYROSCOPE BASED ON SOI WAFER

Mode matching is the key to improve the performance of micro-machined vibrating ring gyroscopes.Mass and stiffness asymmetries can lend to normal modes badly mismatch for gyroscopes fabricated by single-crystal silicon.The mismatch of the normal nodes results in large normal mode frequency split and degraded sensitivity.To address this issue,a Silicon-On-Insulator(SOI) wafer is used to fabricate the sensor chips.Meanwhile,a compensate disk and the backside coated negative photo resist(AZ303) is employed to weaken the Lag and Footing effect during the Deep Reactive Ion Etching(DRIE) process.Test results reveal that frequency split between the normal modes is of less than 10 Hz before the following electronic tuning.Thus,the mode matching of the electromagnetic vibrating ring gyroscope is probable to be realized.

A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer

A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator（SOI） devices. In this new structure, the conventional buried oxide（BOX） in an SOI device is split into two sections： the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer（NPCL）, is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage（BV） is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor（LDMOS） and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance（Ron,sp） is reduced by 69% in comparison to the conventional structure.

Microwave photonic filter with a continuously tunable central frequency using an SOI high-Q microdisk resonator

Utilizing a high-Q microdisk resonator （MDR） on a single silicon-on-insulator （SOI） chip, a compact microwave photonic filter （MPF） with a continuously tunable central frequency is proposed and experimentally demonstrated. Assisted by the optical single side-band （OSSB） modulation, the optical frequency response of the MDR is mapped to the microwave frequency response to form an MPF with a continuously tunable central frequency and a narrow 3-dB bandwidth. In the experiment, using an MDR with a compact size of 20×20 μm^2 and a high Q factor of 1.07×10^5, we obtain a compact MPF with a high rejection ratio of about 40 dB, a 3-dB bandwidth of about 2 GHz, and a frequency tuning range larger than 12 GHz. Our approach may allow the implementation of very compact, low-cost, low-consumption, and integrated notch MPF in a silicon chip.

TEM STUDY ON LOCALIZED RECRYSTALLIZATION SOI

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A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator （SOI） trench lateral double-diffused metal-oxide-semiconductor （LDMOS） is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.

叠层SOI MOSFET不同背栅偏压下的热载流子效应

叠层绝缘体上硅(SOI)器件通过调节背栅偏压来补偿辐照导致的阈值电压退化,对于长期工作在辐射环境中的叠层SOI器件,热载流子效应也是影响其可靠性的重要因素。因此,采用加速老化的方法研究了叠层SOI NMOSFET在不同背栅偏压下的热载流子效应。实验结果表明,在负背栅偏压下有更大的碰撞电离,而电应力后阈值电压的退化却随着背栅偏压的减小而减小。通过二维TCAD仿真进一步分析了不同背栅偏压下的热载流子退化机制,仿真结果表明,背栅偏压在改变碰撞电离率的同时也改变了热电子的注入位置,正背栅偏压下会有更多的热电子注入到离前栅中心近的区域,而在负背栅偏压下则是注入到离前栅中心远的区域,从而导致正背栅偏压下的阈值电压退化更严重。

Silicon-on-nothing MOSFETs fabricated with hydrogen and helium co-implantation

In this paper, a method to fabricate Silicon-on-Nothing （SON） MOSFETs using H^＋ and He^＋ co-implantation is presented. The technique is compatible with conventional CMOS technology and its feasibility has been experimentally demonstrated. SON MOSFETs with 50nm gate length have been fabricated. Compared with the corresponding bulk MOSFETs, the SON MOSFETs show higher on current, reduced leakage current and lower subthreshold slope.

Influence of characteristics' measurement sequence on total ionizing dose effect in PDSOI nMOSFET

The influence of characteristics’ measurement sequence on total ionizing dose effect in partially-depleted SOI nMOSFET is comprehensively studied. We find that measuring the front-gate curves has no influence on total ionizing dose effect.However, the back-gate curves’ measurement has a great influence on total ionizing dose effect due to high electric field in the buried oxide during measuring. In this paper, we analyze their mechanisms and we find that there are three kinds of electrons tunneling mechanisms at the bottom corner of the shallow trench isolation and in the buried oxide during the backgate curves’ measurement, which are: Fowler–Nordheim tunneling, trap-assisted tunneling, and charge-assisted tunneling.The tunneling electrons neutralize the radiation-induced positive trapped charges, which weakens the total ionizing dose effect. As the total ionizing dose level increases, the charge-assisted tunneling is enhanced by the radiation-induced positive trapped charges. Hence, the influence of the back-gate curves’ measurement is enhanced as the total ionizing dose level increases. Different irradiation biases are compared with each other. An appropriate measurement sequence and voltage bias are proposed to eliminate the influence of measurement.

Effects of back gate bias on radio-frequency performance in partially depleted silicon-on-inslator nMOSFETs

The effects of back gate bias(BGEs) on radio-frequency(RF) performances in PD SOI n MOSFETs are presented in this paper. Floating body(FB) device, T-gate body-contact(TB) device, and tunnel diode body-contact(TDBC) device, of which the supply voltages are all 1.2 V, are compared under different back gate biases by different figures of merit, such as cut-off frequency( fT), maximum frequency of oscillation( fmax), etc. Because of the lack of a back gate conducting channel, the drain conductance(gd) of TDBC transistor shows a smaller degradation than those of the others, and the trans-conductance(gm) of TDBC is almost independent of back gate bias. The values of fT of TDBC are also kept nearly constant under different back gate biases. However, RF performances of FB and TB each show a significant degradation when the back gate bias is larger than ～ 20 V. The results indicate that TDBC structures could effectively improve the back gate bias in RF performance.

DISCONTINUOUS GALERKIN TIME DOMAIN METHOD FOR SOI THIN-RIDGE WAVEGUIDE PROBLEM

A novel high-order three-dimensional （3-D） discontinuous Galerkin time domain （DGTD） method based on a normalized formulation of Maxwell＇s equations is developed for modeling and simulating silicon-on-insulator （SOD thin-ridge waveguide. The DGTD method employs unstructured meshes and piecewise high-order polynomials for spatial discretization, and Runge-Kutta methods for time integration. It is found that the numerical results of the leakage loss of SOI thin-ridge waveguide agree well with those of analytical solutions, which proves that the proposed method is an ideal tool for the quantitative analysis for SOI thin-ridge waveguide.

A 10-MHz SOI-Based Face Shear Square Micromechanical Resonator

A 10-MHz face shear （FS） square micro- mechanical resonator based on silicon-on-insulator （SO1） technology is presented in this paper. In order to examine the improvement of quality factor as well as motional resistance Rx in this structure, the center-stem anchor is employed in this study. The benefit of anchoring the square in the center, which is the nodal point, is that the energy losses through the anchor can be minimized. Hence, a quality factor value of 2.0 million and the motional resistance of 8.2 k~ can be obtained with an FS mode resonator via finite element （FE） simulation. The results show the significance of the FS mode in this design, not only in its structure but also in its square-extensional mode and Lame-mode. Additionally, an SOI-based fabrication process is proposed to support the design.

Enhanced radiation-induced narrow channel effects in 0.13-μm PDSOI nMOSFETs with shallow trench isolation

Total ionizing dose responses of different transistor geometries after being irradiated by ^（60）Co γ-rays, in 0.13-μm partially-depleted silicon-on-insulator（PD SOI） technology are investigated. The negative threshold voltage shift in an n-type metal-oxide semiconductor field effect transistor（nMOSFET） is inversely proportional to the channel width due to radiation-induced charges trapped in trench oxide, which is called the radiation-induced narrow channel effect（RINCE）.The analysis based on a charge sharing model and three-dimensional technology computer aided design（TCAD） simulations demonstrate that phenomenon. The radiation-induced leakage currents under different drain biases are also discussed in detail.

SOI基底上制备的用于检测机器人手指接触力的微压阻式力传感器

为了使工业机器人可以稳定、高效地完成夹持任务,设计并制备了三种不同结构的微压阻式力传感器。利用热氧化、硼扩散掺杂、光刻、反应离子刻蚀、物理气相沉积和阳极键合等微电子机械系统(MEMS)加工工艺在绝缘体上硅(SOI)基底上制备出了尺寸均为2 mm×2 mm×0.5 mm的三种微压阻式力传感器。通过封装前后对三种传感器在z方向上的应力灵敏度测试,结果表明第二种传感器的灵敏度较佳,封装前可达0.18 mV/mN,封装后仍可达0.096 mV/mN,仅减少了0.084 mV/mN,仍具有良好的线性关系,输出特性的趋势与预计一致。同时,这三种不同结构的传感器各方向之间的串扰均小于5%,非线性小于满量程的3%。通过封装前后力传感器性能对比,为优化此类传感器设计提供了实验数据,为后续配置在机器人的指尖上实现高效、稳定的操作提供了参考。

SOI微型电场传感器的设计与测试

该文研制了一种新型的基于SOI(Silicon-On-Insulator)微机械加工技术的高性能电场传感器敏感结构。为提高传感器的灵敏度和信噪比,该器件采用侧面屏蔽感应电极的独特设计方案,降低了传感器屏蔽电极的边缘效应;并基于有限元仿真,进一步优化了传感器敏感结构参数。在室温和室内大气压条件下,测试表明,测试量程0～50kV/m,传感器总不确定度优于2%,分辨率为50 V/m。