A comparative study of YBa_2Cu_3O_(7-δ)/YSZ bilayer films deposited on silicon-on-insulator substrates with and without HF pretreatment

Highly epitaxial YBa2Cu3O7-δ （YBCO） and yttria-stabilized zirconia （YSZ） bilayer thin films have been deposited on silicon-on-insulator （SOI） substrates by using in situ pulsed laser deposition （PLD） technique. In the experiment, the native amorphous SiO2 layers on some of the SOI substrates are removed by dipping them in a 10% HF solution for 15 s. Comparing several qualities of films grown on substrates with or without HF pretreatment, such as thin film crystallinity, general surface roughness, temperature dependence of resistance, surface morphology, as well as average crack spacing and crack width, naturally leads to the conclusion that preserving the native SiO2 layer on the surface of the SOI substrate can not only simplify the experimental process but can also achieve fairly high quality YSZ and YBCO thin films.

Substrate bias effects on collector resistance in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

An analytical expression for the co/lector resistance of a novel vertical SiGe heterojunction bipolar transistor （HBT） on thin film silicon-on-insulator （SOI） is obtained with the substrate bias effects being considered. The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate-collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μtm millimeter-wave SiGe SOI BiCMOS devices.

Resistivity and Radio-Frequency Properties of Two-Generation Trap-Rich Silicon-on-Insulator Substrates

Crystal morphologies and resistivity of polysilicon trap-rich layers of two-generation trap-rich silicon-on-insulator（TR-SOI） substrates are studied. It is found that the resistivity of the trap-rich layer of generation 2（TR-G2）is higher than that of generation 1（TR-G1）, although the crystal morphologies of the trap rich layers are the same. In addition, the rf performance of two-generation TR-SOI substrates is investigated by coplanar waveguide lines and inductors. The results show that both the rf loss and the second harmonic distortion of TR-G2 are smaller than those of TR-G1. These results can be attributed to the higher resistivity values of both the trap-rich layer and the high-resistivity silicon（HR-Si） substrate of TR-G2. Moreover, the rf performance of the TR-SOI substrate with thicker buried oxide is slightly better. The second harmonics of various TR-SOI substrates are simulated and evaluated with the harmonic quality factor model as well. It can be predicted that the TR-SOI substrate will see further improvement in rf performance if the resistivities of both the trap-rich layer and HR-Si substrate increase.

The Nonlinear Electronic Transport in Multilayer Graphene on Silicon-on-Insulator Substrates

We conduct a study on the superlinear transport of multilayer graphene channels that partially or completely locate on silicon which is pre-etched by inductively coupled plasma （ICP）. By fabricating a multilayer-graphene field-effect transistor on a Si/SiO2 substrate, we obtain that the superlinearity results from the interaction between the multilayer graphene sheet and the ICP-etched silicon, In addition, the observed superlinear transport of the device is found to be consistent with the prediction of Schwinger＇s mechanism. In the high bias regime, the values of a increase draxnatically from 1.02 to 1.40. The strength of the electric field corresponding to the on-start of electron-hole pair production is calculated to be 5 × 10^4 Vim. Our work provides an experimental observation of the nonlinear transport of the multilayer graphene.

Novel lateral insulated gate bipolar transistor on SOI substrate for optimizing hot-carrier degradation

A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.

Radio-Frequency Characteristics of Partial Dielectric Removal HR-SOI and TR-SOI Substrates

High-resistivity silicon-on-insulator （HR-SOI） and trap-rich high-resistivity silicon-on-insulator （TR-S01） sub- strates have been widely adopted for high-performance rf integrated circuits. Radio-frequency loss and non- linearity characteristics are measured from coplanar waveguide （CPW） t lines fabricated on HR-SOI and TR-SOI substrates. The patterned insulator structure is introduced to reduce loss and non-linearity char- acteristics. A metal-oxide-semiconductor （MOS） CPW circuit model is established to expound the mechanism of reducing the parasitic surface conductance （PSC） effect by combining the semiconductor characteristic anal- ysis （pseudo-MOS and C-V test）. The rf performance of the CPW transmission lines under dc bias supply is also compared. The TR-SOI substrate with the patterned oxide structure sample has the minimum rf loss （〈0.2 dB/mm up to 10 GHz）, the best non-linearity performance, and reductions of 4 dB and 10 dB are compared with the state-of-the-art TR-SOI sample＇s, HD2 and HD3, respectively. It shows the potential application for integrating the two schemes to further suppress the PSC effect.

New Method of Total Ionizing Dose Compact Modeling in Partially Depleted Silicon-on-Insulator MOSFETs

On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with 60Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.

图形化Silicon-on-Insulator衬底上分子束外延生长可动GaN微光栅的研究

GaN材料作为第三代半导体材料,具有宽禁带、直接带隙、耐腐蚀等优点,是一种非常有前景的MOEMS材料。由于GaN的刻蚀目前尚未成熟,因此图形化外延生长法是一种较好的选择。本文基于SOI(silicon-on-insulator)基片,利用硅的微加工技术和图形化GaN分子束外延生长工艺,设计并加工了工作在太赫兹波段的、可以在二维方向上运动的SOI基GaN光栅。光栅周期为16μm,光栅宽度为6μm,峰值位置为25.901μm。通过仿真优化,设计的微驱动器在水平电压220V时,水平方向上的位移为±7.26μm;垂直方向加200V电压时,垂直位移2.5μm。为了研究在图形化SOI衬底上外延生长的InGaN/GaN量子阱薄膜的光学性能,用激光拉曼光谱仪对薄膜进行了光致发光光谱实验。实验结果表明,InGaN/GaN量子阱薄膜具有良好的发光性能,其发光范围为350~500nm,覆盖了紫外光到黄绿光。由于局域态效应与禁带收缩的作用,随着环境温度由10K升高至室温,薄膜的PL光谱的峰位呈现"S"形变化趋势。

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional（2D） Poisson＇s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage（BV） is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer（Q_（ntop）） is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

Metastable Electron Traps in Modified Silicon-on-Insulator Wafer

We perform the total ionizing radiation and electrical stress experiments to investigate the electrical characteristics of the modified silicon-on-insulator（SOI） wafers under different Si ion implantation conditions. It is confirmed that Si implantation into the buried oxide can create deep electron traps with large capture cross section to effectively improve the antiradiation capability of the SOI device. It is first proposed that the metastable electron traps accompanied with Si implantation can be avoided by adjusting the peak location of the Si implantation reasonably.

Fabrication and Characterization of a Single Electron Transistor Based on a Silicon-on-Insulator

A single electron transistor based on a silicon-on-insulator is successfully fabricated with electron-beam nano- lithography, inductively coupled plasma etching, thermal oxidation and other techniques. The unique design of the pattern inversion is used, and the pattern is transferred to be negative in the electron-beam lithography step. The oxidation process is used to form the silicon oxide tunneling barriers, and to further reduce the effective size of the quantum dot. Combinations of these methods offer advantages of good size controllability and accuracy, high reproducibility, low cost, large-area contacts, allowing batch fabrication of single electron transistors and good integration with a radio-frequency tank circuit. The fabricated single electron transistor with a quantum dot about 50nto in diameter is demonstrated to operate at temperatures up to 70K. The charging energy of the Coulomb island is about 12.5meV.

SOI横向二极管击穿特性分析

对硅片直接键合方法制作的 SOI横向二极管的击穿特性在不同条件下进行了测量 ,通过计算机模拟分析了击穿机理 ,从器件的几何尺寸和衬底偏置电压方面 ,提出了提高击穿电压的途径。

基于SOS/SOI绝缘衬底的Si/SiGe HBT设计

着重讨论了衬底阻抗对HBT器件频率性能的劣化机制。基于双口网络理论,定量分析了fT和fm与衬底电阻率的关系;采用SOS/SOI绝缘衬底和自行设计的岛型隔离方法,抑制了绝大多数容性寄生参数;同时,围绕绝缘衬底进行Si/SiGeHBT的横向/纵向结构设计,开发出发射极自对准工艺方法,用于降低接触电阻和一定特征尺寸下的结面积,提高了HBT的频率性能。

SOI衬底和n^+衬底上SiGe HBT的研制

分别在高掺杂的Si衬底和SOI衬底上用超高真空化学汽相淀积(UHV/CVD)系统生长了SiGe/Si外延材料,并采用2μm的工艺制备出SiGe/SiHBT(Heterostructure Bipolar Transistor).使用晶体管图示仪测量晶体管的特性.性能测试表明,在SOI衬底上获得了直流增益β大于300的SiGeHBT,但SOI衬底上的SiGeHBT表现出较严重的自热效应.此外,使用Al电极制备的HBT具有大于0.3V的开启电压,而使用TiAu电极的HBT开启电压远小于该值.对不同衬底上研制的不同电极的SiGeHBT的直流特性进行了比较,并对产生不同特性的原因进行了分析.

基于SOI衬底的射频电感优化设计

比较了SOIRF电感与体硅电感的性能 ,并根据模拟结果分析了电感中空面积 ,电感形状结构 ,金属宽度、间距对SOI电感品质因数Q、自谐振频率、电感量L的影响 ,最后提出了一种基于SOI衬底RF电感的优化设计原则 .以往射频集成电感性能的比较并不固定电感值 。

基于SOI衬底的宽带低损耗声表面波滤波器研究

使用结构为42°Y-X LiTaO_(3)(600 nm)/SiO_(2)(500 nm)/Si的SOI衬底,通过抑制横向模式等优化设计,研制了单端谐振器和声表面波滤波器。经测试,谐振器的谐振频率为1.5 GHz,品质因数(Q)值高达4000;滤波器的中心频率为1370 MHz,插入损耗为-1.2 dB,1 dB带宽为74 MHz,相对带宽达到5.4%,阻带抑制大于40 dB,且温度系数在-55~+85℃时优于-9×10^(-6)/℃。该产品具有高频、宽带、低损耗、低温漂、高阻带抑制的特点,其性能指标优异,具有很好的实用性。

一种新型的SOI MOSFET衬底模型提取方法

衬底寄生网络建模和参数提取,对RF SOI MOSFET器件输出特性的模拟有着非常重要的影响。考虑BOX层引入的体区和Si衬底隔离,将源、体和衬底短接接地,测试栅、漏二端口S参数的传统测试结构,无法准确区分衬底网络影响。提出一种改进的测试结构,通过把SOI MOSFET的漏和源短接为信号输出端、栅为信号输入端,测试栅、漏/源短接二端口S参数的方法,把衬底寄生在二端口S参数中直接体现出来,并开发出一种解析提取衬底网络模型参数的方法,支持SOI MOSFET衬底网络模型的精确建立。采用该方法对一组不同栅指数目的SOI MOSFET进行建模,测量和模型仿真所得S参数在20 GHz频段范围内得到很好吻合。

FABRICATION AND TEST OF AN ELECTROMAGNETIC VIBRATING RING GYROSCOPE BASED ON SOI WAFER

Mode matching is the key to improve the performance of micro-machined vibrating ring gyroscopes.Mass and stiffness asymmetries can lend to normal modes badly mismatch for gyroscopes fabricated by single-crystal silicon.The mismatch of the normal nodes results in large normal mode frequency split and degraded sensitivity.To address this issue,a Silicon-On-Insulator(SOI) wafer is used to fabricate the sensor chips.Meanwhile,a compensate disk and the backside coated negative photo resist(AZ303) is employed to weaken the Lag and Footing effect during the Deep Reactive Ion Etching(DRIE) process.Test results reveal that frequency split between the normal modes is of less than 10 Hz before the following electronic tuning.Thus,the mode matching of the electromagnetic vibrating ring gyroscope is probable to be realized.

用于后栅工艺的SOI-FinFET选择性沟道缩小技术

在FinFET技术中Fin的宽度对器件性能有重要影响。较窄的Fin能够更好地抑制短沟道效应,改善器件亚阈值特性,但同时也导致源漏扩展区寄生电阻增大,驱动电流减小。提出了一种用于FinFET后栅工艺的选择性沟道缩小技术,即在去除多晶硅假栅后,对沟道区露出的Fin进行氢气(含氯基)热退火处理,在减小沟道区Fin的宽度、使沟道区Fin表面光滑的同时,保持源漏扩展区Fin的宽度不变。这种自对准的沟道缩小方法简单有效地解决了亚阈值特性和源漏扩展区寄生电阻对Fin宽要求不一致的问题,并改善了器件的拐角效应。这项工艺集成技术应用于栅长为25 nm^0.5μm的SOI-FinFET器件结构中,并测试得到了良好的器件电学特性。

A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer

A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator（SOI） devices. In this new structure, the conventional buried oxide（BOX） in an SOI device is split into two sections： the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer（NPCL）, is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage（BV） is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor（LDMOS） and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance（Ron,sp） is reduced by 69% in comparison to the conventional structure.