基于0.18μm SOI CMOS工艺设计了一款用于数字相控阵雷达的宽带有源下混频器。该混频器集成了射频、本振放大器、Gilbert混频电路、中频放大器以及ESD保护电路。该芯片可以直接差分输出,亦可经过片外balun合成单端信号后输出。射频和本...基于0.18μm SOI CMOS工艺设计了一款用于数字相控阵雷达的宽带有源下混频器。该混频器集成了射频、本振放大器、Gilbert混频电路、中频放大器以及ESD保护电路。该芯片可以直接差分输出,亦可经过片外balun合成单端信号后输出。射频和本振端口VSWR的测试结果在0.7~4.0GHz范围内均小于2,IF端口的VSWR测试结果在25 MHz^1GHz范围内小于2。当差分输出时,该混频器的功率转换增益为10dB,1dB压缩点输出功率为3.3dBm。电源电压为2.5V,静态电流为64mA,芯片面积仅为1.0mm×0.9mm。展开更多
利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效...利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。展开更多
This paper presents the design of single-pole six-throw （SP6T） RF switch with IBM 0.18 #m SOI CMOS technology, which can be widely used in a wireless communication system with its high performance and low cost. The ...This paper presents the design of single-pole six-throw （SP6T） RF switch with IBM 0.18 #m SOI CMOS technology, which can be widely used in a wireless communication system with its high performance and low cost. The circuit is designed and simulated by using an idea that the total load is divided into six branches and SOI special structures. The insertion loss is less than 0.6 dB, isolation is more than 30 dB, the input power P0.1dB for 0.1 dB compression point is more than 37.5 dBm, IIP3 is more than 70 dBm, the 2nd and the 3rd harmonic compressions are more than 96 dBc, and the control voltage is （＋2.46 V, 0, -2.46 V） in the frequency from 0.1 to 2.7 GHz.展开更多
The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main...The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main driver to satisfy slew rate of output data, receiver includes optimized topology to improve preci- sion of received data. The circuit simulation is based on Cadence’s spectre software and Taiwan Semiconduc- tor Manufacture Corporation’s library of 0.25μm mixed-signal Complementary Metal-Oxide Semiconductor (CMOS) model. The front and post-simulation results reveal that the transceiver designed can transmit and re- ceive high-speed data in 480Mbps, which is in agreement with USB2.0 specification. The chip of physi- cal-layer transceiver has been designed and implemented with 0.25μm standard CMOS technology.展开更多
In-phase/quadrature （I/Q） mismatch is a key problem in zero intermediate frequency （ZIF） receiver architectures. Although integration and careful layout can alleviate I/Q mismatch, circuit and system level calibra...In-phase/quadrature （I/Q） mismatch is a key problem in zero intermediate frequency （ZIF） receiver architectures. Although integration and careful layout can alleviate I/Q mismatch, circuit and system level calibrations are also needed due to process variations and variable operating conditions. The amplitude im- balance between I/Q channels was calibrated using a modified R-2R ladder to achieve fine linear-in-dB variable gain. A downconversion mixer working in the 2,4-GHz band was developed for a wireless local area network （WLAN） ZIF receiver using 0.25μm complementary metal-oxide semiconductor （CMOS）. The twostage mixer configuration relaxes the tradeoff between noise and linearity. Experimental results verify the fine linear-in-dB variable conversion gain of the mixer, which can also be used as part of an automatic gain control （AGC）loop.展开更多
文摘基于0.18μm SOI CMOS工艺设计了一款用于数字相控阵雷达的宽带有源下混频器。该混频器集成了射频、本振放大器、Gilbert混频电路、中频放大器以及ESD保护电路。该芯片可以直接差分输出,亦可经过片外balun合成单端信号后输出。射频和本振端口VSWR的测试结果在0.7~4.0GHz范围内均小于2,IF端口的VSWR测试结果在25 MHz^1GHz范围内小于2。当差分输出时,该混频器的功率转换增益为10dB,1dB压缩点输出功率为3.3dBm。电源电压为2.5V,静态电流为64mA,芯片面积仅为1.0mm×0.9mm。
文摘利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。
基金Project supported by the Zhejiang Provincial Natural Science Foundation of China(No.LZ16F010001)
文摘This paper presents the design of single-pole six-throw （SP6T） RF switch with IBM 0.18 #m SOI CMOS technology, which can be widely used in a wireless communication system with its high performance and low cost. The circuit is designed and simulated by using an idea that the total load is divided into six branches and SOI special structures. The insertion loss is less than 0.6 dB, isolation is more than 30 dB, the input power P0.1dB for 0.1 dB compression point is more than 37.5 dBm, IIP3 is more than 70 dBm, the 2nd and the 3rd harmonic compressions are more than 96 dBc, and the control voltage is （＋2.46 V, 0, -2.46 V） in the frequency from 0.1 to 2.7 GHz.
文摘The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main driver to satisfy slew rate of output data, receiver includes optimized topology to improve preci- sion of received data. The circuit simulation is based on Cadence’s spectre software and Taiwan Semiconduc- tor Manufacture Corporation’s library of 0.25μm mixed-signal Complementary Metal-Oxide Semiconductor (CMOS) model. The front and post-simulation results reveal that the transceiver designed can transmit and re- ceive high-speed data in 480Mbps, which is in agreement with USB2.0 specification. The chip of physi- cal-layer transceiver has been designed and implemented with 0.25μm standard CMOS technology.
文摘In-phase/quadrature （I/Q） mismatch is a key problem in zero intermediate frequency （ZIF） receiver architectures. Although integration and careful layout can alleviate I/Q mismatch, circuit and system level calibrations are also needed due to process variations and variable operating conditions. The amplitude im- balance between I/Q channels was calibrated using a modified R-2R ladder to achieve fine linear-in-dB variable gain. A downconversion mixer working in the 2,4-GHz band was developed for a wireless local area network （WLAN） ZIF receiver using 0.25μm complementary metal-oxide semiconductor （CMOS）. The twostage mixer configuration relaxes the tradeoff between noise and linearity. Experimental results verify the fine linear-in-dB variable conversion gain of the mixer, which can also be used as part of an automatic gain control （AGC）loop.
