绝缘体上硅(Silicon on insulator,SOI)技术在200~400℃高温器件和集成电路方面有着广泛的应用前景,但对于沟道长度≤0.18μm的短沟道器件在200℃以上的高温下阈值电压漂移量达40%以上,漏电流达μA级,无法满足电路设计要求。本文研究了...绝缘体上硅(Silicon on insulator,SOI)技术在200~400℃高温器件和集成电路方面有着广泛的应用前景,但对于沟道长度≤0.18μm的短沟道器件在200℃以上的高温下阈值电压漂移量达40%以上,漏电流达μA级,无法满足电路设计要求。本文研究了基于0.15μm SOI工艺的1.5 V MOS器件电特性在高温下的退化机理和抑制方法,通过增加栅氧厚度、降低阱浓度、调整轻掺杂漏离子注入工艺等优化方法,实现了一种性能良好的短沟道高温SOI CMOS器件,在25~250℃温度范围内,该器件阈值电压漂移量<30%,饱和电流漂移量<15%,漏电流<1 nA/μm。此外采用仿真的方法分析了器件在高温下的漏区电势和电场的变化规律,将栅诱导漏极泄漏电流效应与器件高温漏电流关联起来,从而定性地解释了SOI短沟道器件高温漏电流退化的机理。展开更多
A rearrangeable nonblocking thermo-optic 4×4 switching matrix,which consists of five 2×2 multimode interference-based Mach-Zehnder interferometer(MMI-MZI) switch elements,is designed and fabricated.The minim...A rearrangeable nonblocking thermo-optic 4×4 switching matrix,which consists of five 2×2 multimode interference-based Mach-Zehnder interferometer(MMI-MZI) switch elements,is designed and fabricated.The minimum and maximum excess loss for the matrix are 6.6 and 10.4dB,respectively.The crosstalk in the matrix is measured to be between -12 and -19.8dB.The switching speed of the matrix is less than 30μs.The power consumption for the single switch element is about 330mW.展开更多
The fabrication of Bragg gratings on silicon-on-insulator （SOI） rib waveguides using electron-beam lithography is presented. The grating waveguide is optimally designed for actual photonic integration. Experimental ...The fabrication of Bragg gratings on silicon-on-insulator （SOI） rib waveguides using electron-beam lithography is presented. The grating waveguide is optimally designed for actual photonic integration. Experimental and theoretical evaluations of the Bragg grating are demonstrated. By thinning the SOl device layer and deeply etching the Bragg grating, a large grating coupling coefficient of 30cm^-1 is obtained.展开更多
An ultracompact 3 dB coupler is designed and fabricated in silicon on insulator,based on 1×2 line tapered multimode interference (MMI) coupler.Comparing with the conventional straight MMI coupler,the device is...An ultracompact 3 dB coupler is designed and fabricated in silicon on insulator,based on 1×2 line tapered multimode interference (MMI) coupler.Comparing with the conventional straight MMI coupler,the device is ～40% shorter in length.The device exhibits uniformity of 1 3dB and excess loss of 2 5dB.展开更多
随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了...随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。展开更多
In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3 N4 film as a buried insulator （SOSN） are successfully formed using epitaxial layer transfer technology for the first ti...In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3 N4 film as a buried insulator （SOSN） are successfully formed using epitaxial layer transfer technology for the first time. The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile. Experiment results show that the buried Si3 N4 layer is amorphous and the new SOI material has good structural and electrical properties. The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOSN can effectively mitigate the selfheating penalty. The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.展开更多
An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, wh...An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional（2D） Poisson＇s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage（BV） is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer（Q_（ntop）） is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.展开更多
文摘绝缘体上硅(Silicon on insulator,SOI)技术在200~400℃高温器件和集成电路方面有着广泛的应用前景,但对于沟道长度≤0.18μm的短沟道器件在200℃以上的高温下阈值电压漂移量达40%以上,漏电流达μA级,无法满足电路设计要求。本文研究了基于0.15μm SOI工艺的1.5 V MOS器件电特性在高温下的退化机理和抑制方法,通过增加栅氧厚度、降低阱浓度、调整轻掺杂漏离子注入工艺等优化方法,实现了一种性能良好的短沟道高温SOI CMOS器件,在25~250℃温度范围内,该器件阈值电压漂移量<30%,饱和电流漂移量<15%,漏电流<1 nA/μm。此外采用仿真的方法分析了器件在高温下的漏区电势和电场的变化规律,将栅诱导漏极泄漏电流效应与器件高温漏电流关联起来,从而定性地解释了SOI短沟道器件高温漏电流退化的机理。
文摘A rearrangeable nonblocking thermo-optic 4×4 switching matrix,which consists of five 2×2 multimode interference-based Mach-Zehnder interferometer(MMI-MZI) switch elements,is designed and fabricated.The minimum and maximum excess loss for the matrix are 6.6 and 10.4dB,respectively.The crosstalk in the matrix is measured to be between -12 and -19.8dB.The switching speed of the matrix is less than 30μs.The power consumption for the single switch element is about 330mW.
文摘The fabrication of Bragg gratings on silicon-on-insulator （SOI） rib waveguides using electron-beam lithography is presented. The grating waveguide is optimally designed for actual photonic integration. Experimental and theoretical evaluations of the Bragg grating are demonstrated. By thinning the SOl device layer and deeply etching the Bragg grating, a large grating coupling coefficient of 30cm^-1 is obtained.
文摘An ultracompact 3 dB coupler is designed and fabricated in silicon on insulator,based on 1×2 line tapered multimode interference (MMI) coupler.Comparing with the conventional straight MMI coupler,the device is ～40% shorter in length.The device exhibits uniformity of 1 3dB and excess loss of 2 5dB.
文摘随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。
文摘In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3 N4 film as a buried insulator （SOSN） are successfully formed using epitaxial layer transfer technology for the first time. The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile. Experiment results show that the buried Si3 N4 layer is amorphous and the new SOI material has good structural and electrical properties. The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOSN can effectively mitigate the selfheating penalty. The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.
基金Project supported by the National Natural Science Foundation of China(Grant No.61376080)the Natural Science Foundation of Guangdong Province,China(Grant No.2014A030313736)the Fundamental Research Funds for the Central Universities,China(Grant No.ZYGX2013J030)
文摘An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional（2D） Poisson＇s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage（BV） is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer（Q_（ntop）） is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.
