Fabrication and Characteristics of a Si-Based Single Electron Transistor

Si based single electron transistor (SET) is fabricated successfully on p type SIMOX substrate,based on electron beam (EB) lithography,reactive ion etching (RIE) and thermal oxidation.In particular,using thermal oxidation and etching off the oxide layer,a one dimensional Si quantum wire can be converted into several quantum dots inside quantum wire in connection with the source and drain regions.The differential conductance (d I ds /d V ds ) oscillations and the Coulomb staircases in the source drain current ( I ds ) are shown clearly dependent on the source drain voltage at 5 3K.The I ds V gs (gate voltage) oscillations are observed from the I ds V gs characteristics as a function of V gs at different temperatures and various values of V ds .For a SET whose total capacitance is about 9 16aF,the I ds V gs oscillations can be observed at 77K.

Detection of Terahertz Photon by GaAs-Based Single Electron Transistor at Low Temperatures

A reproducible terahertz （THz） photocurrent was observed at low temperatures in a Schottky wrap gate single electron transistor with a normal-incident of a CH3OH gas laser with the frequency 2.54THz. The change of source-drain current induced by THz photons shows that a satellite peak is generated beside the resonance peak. THz photon energy can be characterized by the difference of gate voltage positions between the resonance peak and satellite peak. This indicates that the satellite peak exactly results from the THz photon-assisted tunneling. Both experimental results and theoretical analysis show that a narrow spacing of double barriers is more effective for the enhancement of THz response.

Single-electron transport through single and coupling dopant atoms in silicon junctionless nanowire transistor

We investigated single-electron tunneling through single and coupling dopant-induced quantum dots(QDs) in silicon junctionless nanowire transistor(JNT) by varying temperatures and bias voltages. We observed that two possible charge states of the isolated QD confined in the axis of the initial narrowest channel are successively occupied as the temperature increases above 30 K. The resonance states of the double single-electron peaks emerge below the Hubbard band, at which several subpeaks are clearly observed respectively in the double oscillated current peaks due to the coupling of the QDs in the atomic scale channel. The electric field of bias voltage between the source and the drain could remarkably enhance the tunneling possibility of the single-electron current and the coupling strength of several dopant atoms. This finding demonstrates that silicon JNTs are the promising potential candidates to realize the single dopant atom transistors operating at room temperature.

Fabrication and Characterization of a Single Electron Transistor Based on a Silicon-on-Insulator

A single electron transistor based on a silicon-on-insulator is successfully fabricated with electron-beam nano- lithography, inductively coupled plasma etching, thermal oxidation and other techniques. The unique design of the pattern inversion is used, and the pattern is transferred to be negative in the electron-beam lithography step. The oxidation process is used to form the silicon oxide tunneling barriers, and to further reduce the effective size of the quantum dot. Combinations of these methods offer advantages of good size controllability and accuracy, high reproducibility, low cost, large-area contacts, allowing batch fabrication of single electron transistors and good integration with a radio-frequency tank circuit. The fabricated single electron transistor with a quantum dot about 50nto in diameter is demonstrated to operate at temperatures up to 70K. The charging energy of the Coulomb island is about 12.5meV.

A Silicon Cluster Based Single Electron Transistor with Potential Room-Temperature Switching

We demonstrate the fabrication of a single electron transistor device based on a single ultra-small silicon quantum dot connected to a gold break junction with a nanometer scale separation. The gold break junction is created through a controllable electromigration process and the individual silicon quantum dot in the junction is deter- mined to be a Si 170 cluster. Differential conductance as a function of the bias and gate voltage clearly shows the Coulomb diamond which confirms that the transport is dominated by a single silicon quantum dot. It is found that the charging energy can be as large as 300meV, which is a result of the large capacitance of a small silicon quantum dot （-1.8 nm）. This large Coulomb interaction can potentially enable a single electron transistor to work at room temperature. The level spacing of the excited state can be as large as 10meV, which enables us to manipulate individual spin via an external magnetic field. The resulting Zeeman splitting is measured and the g factor of 2.3 is obtained, suggesting relatively weak electron-electron interaction in the silicon quantum dot which is beneficial for spin coherence time.

New Model for Drain and Gate Current of Single-Electron Transistor at High Temperature

We propose a novel analytical model to describe the drain-source current as well as gate-source of single-electron transistors (SETs) at high temperature. Our model consists on summing the tunnel current and thermionic contribution. This model will be compared with another model.

A Model of a Single Electron Transistor of Metallic Tunneling Junctions and Its Validation

Based on the orthodox theory,a model of a single electron transistor （SET） of metallic tunneling junctions is built using the master equation method. Several parameters of the device, such as capacitance, resistance and temperature,are input into the model and thus the I-V curves are attained. These curves are consistent with those from other experiments; therefore, the model is verified. However, there still exists a difference between simulated results and experimental results,mainly comes from the stationary case of the master equation. In other words, precision of simulated results would be increased if the transient case of the master equation is considered. Moreover, the current increases exponentially at higher drain voltages, which is due to the fact that the barrier suppression is caused by the image charge potential.

A Hybrid Random Number Generator Using Single Electron Tunneling Junctions and MOS Transistors

This paper proposes a novel single electron random number generator （RNG）. The generator consists of multiple tunneling junctions （MTJ） and a hybrid single electron transistor （SET）/MOS output circuit. It is an oscillator-based RNG. MTJ is used to implement a high-frequency oscillator, which uses the inherent physical randomness in tunneling events of the MTJ to achieve large frequency drift. The hybrid SET and MOS output circuit is used to amplify and buffer the output signal of the MTJ oscillator. The RNG circuit generates high-quality random digital sequences with a simple structure. The operation speed of this circuit is as high as 1GHz. The circuit also has good driven capability and low power dissipation. This novel random number generator is a promising device for future cryptographic systems and communication applications.

带数字驱动的DC-18 GHz单刀三掷开关设计

设计了一款带数字驱动的DC-18 GHz单刀三掷开关(Single-Pole Three-Throw,SP3T)芯片。该芯片集成了单刀三掷开关和数字驱动器。单刀三掷开关由2个单刀双掷开关级联组成。单刀双掷开关采用吸收式开关结构,可以实现更好的关态驻波比。驱动电路采用直接耦合场效应晶体管逻辑(Direct Coupled Field Effect Transistor Logic,DCFL)式逻辑电路,具有结构简单、功耗低的优点。版图经过合理布局后,芯片尺寸为1.5 mm×2 mm。测试结果表明:在DC-18 GHz频段内,芯片插入损耗小于3.5 dB,隔离度大于50 dB。芯片采用5 V/0 V逻辑控制,开关速度小于8 ns,1 dB压缩输入功率23 dBm。

Influence of Ⅴ/Ⅲ ratio on the structural and photoluminescence properties of In_(0.52) AlAs/In_(0.53) GaAs metamorphic high electron mobility transistor grown by molecular beam epitaxy

A series of metamorphic high electron mobility transistors （MMHEMTs） with different Ⅴ/Ⅲ flux ratios are grown on CaAs （001） substrates by molecular beam epitaxy （MBE）. The samples are analysed by using atomic force microscopy （AFM）, Hall measurement, and low temperature photoluminescence （PL）. The optimum Ⅴ/Ⅲ ratio in a range from 15 to 60 for the growth of MMHEMTs is found to be around 40. At this ratio, the root mean square （RMS） roughness of the material is only 2.02 nm; a room-temperature mobility and a sheet electron density are obtained to be 10610.0cm^2/（V.s） and 3.26×10^12cm^-2 respectively. These results are equivalent to those obtained for the same structure grown on InP substrate. There are two peaks in the PL spectrum of the structure, corresponding to two sub-energy levels of the In0.53Ga0.47As quantum well. It is found that the photoluminescence intensities of the two peaks vary with the Ⅴ/Ⅲ ratio, for which the reasons are discussed.

Annealing effect of platinum-incorporated nanowires created by focused ion/electron-beam-induced deposition

Focused ion-beam-induced deposition （FIBID） and focused electron-beam-induced deposition （FEBID） are conve- nient and useful in nanodevice fabrication. Since the deposition is from the organometallic platinum precursor, the con- ductive lines directly written by focused ion-beam （FIB） and focused electron-beam （FEB） are carbon-rich materials. We discuss an alternative approach to enhancing the platinum content and improving the conductivity of the conductive leads produced by FIBID and FEBID, namely an annealing treatment. Annealing in pure oxygen at 500 ℃ for 30 min enhances the platinum content values from ~ 18% to 30% and ~ 50% to 90% of FIBID and FEBID, respectively. Moreover, we find that thin films will be formed in the FIBID and FEBID processes. The annealing treatment is helpful to avoid the current leakage caused by these thin films. A single electron transistor is fabricated by FEBID and the current-voltage curve shows the Coulomb blockade effect.

Organic single-crystal light-emitting transistors with external quantum efficiency over 20%

Organic light-emitting transistors(OLETs)have attracted increasing attention because of their potential applications in next-generation displays and high-energy operating devices.However,the simultaneous achievement of high luminescent efficiency and carrier mobility in organic semiconductors remains challenging because the localized excitons are advantageous for light emission,whereas the delocalized carriers are beneficial for efficient charge migration.Herein,we report an organic single crystal of a cyano-substituted styrene derivative with balanced mobility yielding a record-high external quantum efficiency of 20.5%in OLETs.Temperature-dependent I–V curves and electronic structure analyses based on firstprinciples calculations were performed to disclose the underlying mechanism as a band transport,which provides an efficient way to achieve high quantum efficiency in OLETs.

基于GaAs E/D PHEMT工艺的Ku波段双通道幅相控制多功能芯片

基于GaAs增强/耗尽型赝配高电子迁移率晶体管(E/D PHEMT)工艺设计了一款14~18 GHz的双通道多功能芯片。芯片集成了单刀双掷(SPDT)开关、6 bit数控移相器、4 bit数控衰减器和增益补偿放大器。采用正压控制开关以减小控制位数;优化移相、衰减和放大等电路拓扑结构,以获得良好的幅相特性;采用紧凑布局、双通道对称的版图设计,以实现小尺寸和高性能。测试结果表明,+5 V电压下,接收通道增益大于3 dB,1 dB压缩点输出功率大于8 dBm;发射通道增益大于1 dB,1 dB压缩点输出功率大于2 dBm;64态移相均方根误差小于2.5°,16态衰减均方根误差小于0.3 dB,芯片尺寸为3.90 mm×2.25 mm。该多功能芯片可实现对射频信号幅度和相位的高精度控制,可广泛应用于微波收发模块。

单电子晶体管I-V特性数值分析

在单电子晶体管的正统理论的基础上 ,建立了平稳条件下I V特性的数值分析方法 .应用该方法计算和分析了温度和栅压对单电子晶体管I V 特性的影响 ,研究了隧道结电阻对于库仑台阶及电导振荡的影响 ,分析了单电子现象产生的条件 .

一种新型单电子-MOS晶体管混合的半加器电路

基于单电子晶体管的I-V特性和MOS晶体管的逻辑电路设计思想,提出了1个单电子晶体管和MOS晶体管混合的反相器电路,进而推导出其它基本逻辑门电路,并最终实现了一个半加器电路。通过比较单电子晶体管和MOS晶体管两者的混合与纯CMOS晶体管实现的半加器电路,元器件数目得到了减少,电路结构得到简化,且电路的静态功耗降低。SPICE验证了电路设计的正确性。

基于R-SET结构的逻辑门电路和触发器设计

提出一种基于单电子晶体管的新型电路结构——R-SET结构,并从R-SET结构的反相器着手对该结构电路的工作原理和性能进行了分析.构造出基于R-SET结构的或非门、一位数值比较器、SR锁存器和D触发器.通过对各电路进行SPICE仿真,验证了各电路的正确性.最后对R-SET和互补型SET 2种结构的D触发器进行性能比较,得出R-SET结构的D触发器具有结构简单,功耗低,延时小的特点.

基于GaN HEMT的双向DC-DC变换器系统损耗分析

为减小氮化镓高电子迁移率晶体管(GaN HEMT)的全桥双向DC-DC变换器(DAB)系统损耗模型与实际运行损耗所存在的偏差,考虑GaN HEMT中寄生参数对DAB系统动态开关过程的影响,建立了精细化DAB系统损耗模型;在单移相控制(SPS)工作模式下,分析了GaN HEMT的开关损耗、通态损耗、隔离变压器以及电感损耗,给出了不同工作阶段GaN HEMT的通态损耗、变压器的铜损耗和铁损耗的计算方法;搭建了DAB系统损耗模型仿真系统。实验结果表明:所建立的精细化损耗模型较实验损耗仅差约0.71%,可用于系统实际损耗的分析。

遗传算法在单电子器件Ⅰ-V特性的半经典拟合中的应用

本文在单电子器件半经典的双隧道结模型的基础上，采用遗传算法通过对主方程的数值求解，对Ａｕ纳米粒子组装体系的库仑台阶现象进行了拟合．我们发现该算法的拟会结果效果很好．

单电子晶体管I-V特性数学建模

基于正统单电子理论,提出了单电子晶体管的I-V特性数学模型。该模型的优点是:它由实际物理参数直接获得;支持双栅极工作,更利于逻辑电路应用。I-V特性和跨导仿真结果证实了它的准确性。

基于SET/MOS混合结构的4-2编码器设计

基于单电子晶体管(SET)的库仑振荡效应、多栅输入特性和相移特性,实现了SET/MOS混合结构的或门逻辑,并利用该或门逻辑实现了4-2编码器。利用HSPICE对所设计电路进行仿真验证,仿真结果表明该电路能够实现4-2编码器的编码功能。与纯CMOS编码器相比,该SET/MOS混合电路仅由2个PMOS管、2个NMOS管和2个SET构成,具有结构简单、尺寸小、集成度高的优点。