Single event upset induced multi-block error and its mitigation strategy for SRAM-based FPGA

According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analyzing the place and route result,the paper points out that the essence of SEU-MBE is that some important modules exceed the safe internal distance.Two approaches,area constraint method(ACM) and incremental route algorithm(IRA),are proposed,which can reduce the error rate by manipulating programmable switch matrix and interconnection points within FPGA route resource.Fault injection experiments indicate that error detection rate is above 98.6% for both strategies,and FPGA resources increment and performance penalty are around 10%.

An advanced SEU tolerant latch based on error detection

This paper proposes a latch that can mitigate SEUs via an error detection circuit.The error detection circuit is hardened by a C-element and a stacked PMOS.In the hold state,a particle strikes the latch or the error detection circuit may cause a fault logic state of the circuit.The error detection circuit can detect the upset node in the latch and the fault output will be corrected.The upset node in the error detection circuit can be corrected by the C-element.The power dissipation and propagation delay of the proposed latch are analyzed by HSPICE simulations.The proposed latch consumes about 77.5%less energy and 33.1%less propagation delay than the triple modular redundancy（TMR）latch.Simulation results demonstrate that the proposed latch can mitigate SEU effectively.