Sensitivity investigation of 100-MeV proton irradiation to SiGe HBT single event effect

The single event effect(SEE) sensitivity of silicon–germanium heterojunction bipolar transistor(Si Ge HBT) irradiated by 100-Me V proton is investigated. The simulation results indicate that the most sensitive position of the Si Ge HBT device is the emitter center, where the protons pass through the larger collector-substrate(CS) junction. Furthermore, in this work the experimental studies are also carried out by using 100-Me V proton. In order to consider the influence of temperature on SEE, both simulation and experiment are conducted at a temperature of 93 K. At a cryogenic temperature, the carrier mobility increases, which leads to higher transient current peaks, but the duration of the current decreases significantly.Notably, at the same proton flux, there is only one single event transient(SET) that occurs at 93 K. Thus, the radiation hard ability of the device increases at cryogenic temperatures. The simulation results are found to be qualitatively consistent with the experimental results of 100-Me V protons. To further evaluate the tolerance of the device, the influence of proton on Si Ge HBT after gamma-ray(^(60)Coγ) irradiation is investigated. As a result, as the cumulative dose increases, the introduction of traps results in a significant reduction in both the peak value and duration of the transient currents.

Sensitivity study of the SiGe heterojunction bipolar transistor single event effect based on pulsed laser and technology computer-aided design simulation

The single event effect of a silicon–germanium heterojunction bipolar transistor(SiGe HBT) was thoroughly investigated. By considering the worst bias condition, the sensitive area of the proposed device was scanned with a pulsed laser.With variation of the collector bias and pulsed laser incident energy, the single event transient of the SiGe HBT was studied.Moreover, the single event transient produced by laser irradiation at a wavelength of 532 nm was more pronounced than at a wavelength of 1064 nm. Finally, the impact of the equivalent linear energy transfer of the 1064 nm pulsed laser on the single event transient was qualitatively examined by performing technology computer-aided design simulations, and a good consistency between the experimental data and the simulated outcomes was attained.

Investigation of single event effect in 28-nm system-on-chip with multi patterns

Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing, and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace environment were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case.

Influence of Tilted Angle on Effective Linear Energy Transfer in Single Event Effect Tests for Integrated Circuits at 130 nm Technology Node

A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130 nm CMOS bulk Si and silicon-on-insulator(SOI) technologies. The effectiveness of linear energy transfer(LET) with a tilted ion beam at the 130 nm technology node is obtained. Tests of tilted angles θ=0°,30°and 60°with respect to the normal direction are performed under heav.y-ion Kr with certain power whose LET is about 40 MeVcm^2/mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ, furthermore the effective LET for SOI is more closely in inverse proportion to cos θ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cos 0 very well, which is also specifically explained.

Novel Fault Detection Optimization Algorithm for Single Event Effect system Based on Multi-information Entropy Fusion

Fault detection caused by single event effect( SEE) in system was studied,and an improved fault detection algorithm by fusing multi-information entropy for detecting soft error was proposed based on multi-objective detection approach and classification management method. In the improved fault detection algorithm, the analysis model of posteriori information with corresponding multi-fault alternative detection points was formulated through correlation information matrix, and the maximum incremental information entropy was chosen as the classification principle for the optimal detection points. A system design example was given to prove the rationality and feasibility of this algorithm.This fault detection algorithm can achieve the purpose of fault detection and resource configuration with high efficiency.

Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

The variations of single event transient(SET)pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor(Fin FET)inverter chains with different driven strengths are measured at different temperatures.Three-dimensional(3D)technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature.Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk Fin FET technology,resulting in the increase of SET pulse width.On the other hand,the increase of inverter driven strength will change the layout topology,which has a complex influence on the SET temperature effects of Fin FET inverter chains.The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

Mechanisms of atmospheric neutron-induced single event upsets in nanometric SOI and bulk SRAM devices based on experiment-verified simulation tool

In this paper, a simulation tool named the neutron-induced single event effect predictive platform(NSEEP^2) is proposed to reveal the mechanism of atmospheric neutron-induced single event effect(SEE) in an electronic device, based on heavy-ion data and Monte-Carlo neutron transport simulation. The detailed metallization architecture and sensitive volume topology of a nanometric static random access memory(SRAM) device can be considered to calculate the real-time soft error rate(RTSER) in the applied environment accurately. The validity of this tool is verified by real-time experimental results. In addition, based on the NSEEP^2, RTSERs of 90 nm–32 nm silicon on insulator(SOI) and bulk SRAM device under various ambient conditions are predicted and analyzed to evaluate the neutron SEE sensitivity and reveal the underlying mechanism. It is found that as the feature size shrinks, the change trends of neutron SEE sensitivity of bulk and SOI technologies are opposite, which can be attributed to the different MBU performances. The RTSER of bulk technology is always 2.8–64 times higher than that of SOI technology, depending on the technology node, solar activity, and flight height.

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

With the critical charge reduced to generate a single event effect(SEE) and high working frequency for a nanometer integrated circuit,the single event effect(SET) becomes increasingly serious for high performance SOC and DSP chips.To analyze the radiation-hardened method of SET for the nanometer integrated circuit,the n^+ guard ring and p^+ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library.The weakest driving capacity inverter cell was used to evaluate the single event transient(SET) pulse-width distribution.We employed a dual-lane measurement circuit to get more accurate SET'S pulsewidth.Six kinds of ions,which provide LETs of 12.5,22.5,32.5,42,63,and 79.5 MeV·cm^2/mg,respectively,have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory.The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LET_(eff) from 12.5 MeV·cm^2/mg to 79.5 MeV·cm^2/mg and the pulse-width presents saturation tendency when the effective linear energy transfer(LET_(eff)) value is larger than 40 MeV·cm^2/mg.The test results also show that the hardened commercial standard cell's pulse-width concentrates on 33 to 264 ps,which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.

AVAILABILITY MODEL FOR SELF TEST AND REPAIR IN FAULT TOLERANT FPGA-BASED SYSTEMS

Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.