An online fast multi-track locating algorithm for high-resolution single-event effect test platform

To improve the efficiency and accuracy of single-event effect(SEE)research at the Heavy Ion Research Facility at Lanzhou,Hi’Beam-SEE must precisely localize the position at which each heavy ion hitting the integrated circuit(IC)causes SEE.In this study,we propose a fast multi-track location(FML)method based on deep learning to locate the position of each particle track with high speed and accuracy.FML can process a vast amount of data supplied by Hi’Beam-SEE online,revealing sensitive areas in real time.FML is a slot-based object-centric encoder-decoder structure in which each slot can learn the location information of each track in the image.To make the method more accurate for real data,we designed an algorithm to generate a simulated dataset with a distribution similar to that of the real data,which was then used to train the model.Extensive comparison experiments demonstrated that the FML method,which has the best performance on simulated datasets,has high accuracy on real datasets as well.In particular,FML can reach 238 fps and a standard error of 1.6237μm.This study discusses the design and performance of FML.

Temperature dependence of single-event transients in SiGe heterojunction bipolar transistors for cryogenic applications

We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors(SiGe HBTs)can change with decreasing temperature from+20℃to-180℃.This is accomplished by using a new well-designed cryogenic experimental system suitable for a pulsed-laser platform.Firstly,when the temperature drops from+20℃to-140℃,the increased carrier mobility drives a slight increase in transient amplitude.However,as the temperature decreases further below-140℃,the carrier freeze-out brings about an inflection point,which means the transient amplitude will decrease at cryogenic temperatures.To better understand this result,we analytically calculate the ionization rates of various dopants at different temperatures based on Altermatt's new incomplete ionization model.The parasitic resistivities with temperature on the charge-collection pathway are extracted by a two-dimensional(2D)TCAD process simulation.In addition,we investigate the impact of temperature on the novel electron-injection process from emitter to base under different bias conditions.The increase of the emitter-base junction's barrier height at low temperatures could suppress this electron-injection phenomenon.We have also optimized the built-in voltage equations of a high current compact model(HICUM)by introducing the impact of incomplete ionization.The present results and methods could provide a new reference for effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures,and could provide a new evidence of the potential of SiGe technology in applications in extreme cryogenic environments.

Investigation of maximum proton energy for qualified ground based evaluation of single-event effects in SRAM devices

Existing standards show a clear discrepancy in the specification of the maximum proton energy for qualified ground-based evaluation of single-event effects,which can range from 180 to 500 MeV. This work finds that the threshold linear energy transfer of a tested device is a critical parameter for determining the maximum proton energy. The inner mechanisms are further revealed. Highenergy deposition events(>10 MeV) in sensitive volumes are attributed to the interaction between protons and the tungsten vias in the metallization layers.

Single-event effects induced by medium-energy protons in 28 nm system-on-chip

Single-event effects(SEEs)induced by mediumenergy protons in a 28 nm system-on-chip(SoC)were investigated at the China Institute of Atomic Energy.An on-chip memory block was irradiated with 90 MeV and 70 MeV protons,respectively.Single-bit upset and multicell upset events were observed,and an uppermost number of nine upset cells were discovered in the 90 MeV proton irradiation test.The results indicate that the SEE sensitivities of the 28 nm SoC to the 90 MeV and 70 MeV protons were similar.Cosmic Ray Effects on Micro-Electronics Monte Carlo simulations were analyzed,and it demonstrates that protons can induce effects in a 28 nm SoC if their energies are greater than 1.4 MeV and that the lowest corresponding linear energy transfer was 0.142 MeV cm^2 mg^-1.The similarities and discrepancies of the SEEs induced by the 90 MeV and 70 MeV protons were analyzed.

Prototype of single-event effect localization system with CMOS pixel sensor

The single-event effect(SEE) is a serious threat to electronics in radiation environments. The most important issue in radiation-hardening studies is the localization of the sensitive region in electronics to the SEE. To solve this problem, a prototype based on a complementary metal oxide semiconductor(CMOS) pixel sensor, i.e., TopmetalM, was designed for SEE localization. A beam test was performed on the prototype at the radiation terminal of the Heavy Ion Research Facility in Lanzhou(HIRFL). The results indicated that the inherent deflection angle of the prototype to the beam was 1.7°, and the angular resolution was 0.6°. The prototype localized heavy ions with a position resolution of 3.4 μm.

Analysis of single-event transient sensitivity in fully depleted silicon-on-insulator MOSFETs

Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.

Single-event-effect propagation investigation on nanoscale system on chip by applying heavy-ion microbeam and event tree analysis

The propagation of single-event effects(SEEs)on a Xilinx Zynq-7000 system on chip(SoC)was inves-tigated using heavy-ion microbeam radiation.The irradia-tion results reveal several functional blocks’sensitivity locations and cross sections,for instance,the arithmetic logic unit,register,D-cache,and peripheral,while irradi-ating the on-chip memory(OCM)region.Moreover,event tree analysis was executed based on the obtained microbeam irradiation results.This study quantitatively assesses the probabilities of SEE propagation from the OCM to other blocks in the SoC.

Catalytic Cracking of Cycloparaffins Admixed with Olefins:1. Single-Event Microkinetic(SEMK) Modeling

Single-event microkinetic(SEMK) model of the catalytic cracking of methylcyclohexane admixed with 1-octene over REUSY zeolites at 693 K—753 K in the absence of coke formation is enhanced. To keep consistency with the wellknown carbenium ion chemistry, hydride transfer forming and consuming allylic carbenium ions in the aromatization of cycloparaffins are further investigated and differentiated. The reversibility of endocyclic β-scission and cyclization reactions is refined by accounting explicitly for the reacting olefins and resulting cycloparaffins in the corresponding thermodynamics. 24 activation energies for the reactions involved in the cracking of cycloparaffins are obtained by the regression of 15 sets of experimental data upon taking the resulting 37 main cracking products, i. e., responses into account. The enhanced SEMK model can adequately describe the catalytic behavior of 37 main products with conversion and temperature.

Scaling effects of single-event gate rupture in thin oxides

The dynamics of the excess carriers generated by incident heavy ions are considered in both SiO2 and Si substrate. Influences of the initial radius of the charge track, surface potential decrease, external electric field, and the LET value of the incident ion on internal electric field buildup are analyzed separately. Considering the mechanisms of recombination, impact ionization, and bandgap tunneling, models are verified by using published experimental data. Moreover, the scaling effects of single-event gate rupture in thin gate oxides are studied, with the feature size of the MOS device down to 90 nm. The walue of the total electric field decreases rapidly along with the decrease of oxide thickness in the first period （1 2 nm to 3.3 nm）, and then increases a little when the gate oxide becomes thinner and thinner （3.3 nm to 1.8 nm）.

Catalytic Cracking of Cycloparaffins Admixed with Olefins:2. Single-Event Microkinetic(SEMK) Assessment

The developed SEMK model is used to provide an insight into the contribution of individual reactions in the cracking of methylcyclohexane as well as the site coverage by various carbenium ions. The preferred reaction pathways for the conversion of methylcyclohexane are hydride transfer reactions followed by PCP-isomerizations, deprotonation and endocyclic β-scission, accounting for 61%, 22% and 12% of its disappearance, respectively, at 693 K and 30% conversion of methylcyclohexane. Protolysis plays a minor role in the cracking of methylcyclohexane. Once cyclic diolefins are formed, all of them can be instantaneously transformed to aromatics, which are easily interconverted via disproportionation. Judging from the carbenium ion concentrations it is evident that, at the investigated operating conditions, less than 5% of the acid sites are covered by carbenium ions, less than 2% of which corresponds to cyclic type species including allylic ones.

Mechanism of single-event transient pulse quenching between dummy gate isolated logic nodes

As integrated circuits scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes.The so-called single-event transient（SET） pulse quenching induced by single-event charge sharing collection has been widely studied. In this paper, SET pulse quenching enhancement is found in dummy gate isolated adjacent logic nodes compared with that isolated by the common shallow trench isolation（STI）. The physical mechanism is studied in depth and this isolation technique is explored for SET mitigation in combinational standard cells. Three-dimensional（3D） technology computer-aided design simulation（TCAD） results show that this technique can achieve efficient SET mitigation.

Impact of proton-induced alteration of carrier lifetime on single-event transient in SiGe heterojunction bipolar transistor

This paper presents an investigation into the impact of proton-induced alteration of carrier lifetime on the singleevent transient(SET) caused by heavy ions in silicon–germanium heterojunction bipolar transistor(SiGe HBT).The ioninduced current transients and integrated charge collections under different proton fluences are obtained based on technology computer-aided design(TCAD) simulation.The results indicate that the impact of carrier lifetime alteration is determined by the dominating charge collection mechanism at the ion incident position and only the long-time diffusion process is affected.With a proton fluence of 5 × 1013 cm-2, almost no change is found in the transient feature, and the charge collection of events happened in the region enclosed by deep trench isolation(DTI), where prompt funneling collection is the dominating mechanism.Meanwhile, for the events happening outside DTI where diffusion dominates the collection process, the peak value and the duration of the ion-induced current transient both decrease with increasing proton fluence, leading to a great decrease in charge collection.

Development of Contactless Method of the DUT Heating during Single-Event Effect Tests

This paper presents two approaches to perform the electronic device heating during radiation hardness assurance tests.Commonly used conductive heating approach is compared with contactless laser-based approach,characteristics and limitations of these methods are described.Experimental results for temperature dependence of single-event latchup(SEL)cross-section during heavy ion irradiation along with some aspects of physics-based numerical simulation of heat transfer processes are presented.

Experimental and simulation studies of single-event transient in partially depleted SOI MOSFET

In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET sensitive than the other regions in PD-SOI devices.We use ISE 3D simulation tools to analyze the SET response when different regions of the device are hit. Then, we discuss in detail the characteristics of transient currents and the electrostatic potential distribution change in devices after irradiation. Finally, we analyze the parasitic bipolar junction transistor（p-BJT） effect by performing both a laser test and simulations.

平板显示器功率驱动芯片的Latch-up及克服方法

详细分析了平板显示器驱动芯片中的Latch-up现象,在此基础上采用了一种克服Latch-up的方法:在低压部分增加多子保护环,在高低压之间增加少子保护环。借助TCAD软件详细研究了少子环位置及宽度对抗Latch-up效果的影响。实验结果证明,采用该方法可以有效地克服功率集成电路的Latch-up现象。

Comparative research on “high currents” induced by single event latch-up and transient-induced latch-up

By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of single event latch-up （SEL） and transient-induced latch-up （TLU） are studied, respectively, for a 12-bit complementary metal--oxide semiconductor （CMOS） analog-to-digital converter. Furthermore, the sameness and difference in physical mechanism between ＂high current＂ induced by SEL and that by TLU are disclosed in this paper. The results show that the minority carrier diffusion in the PNPN structure of the CMOS device which initiates the active parasitic NPN and PNP transistors is the common reason for the ＂high current＂ induced by SEL and for that by TLU, However, for SEL, the minority carder diffusion is induced by the ionizing radiation, and an underdamped sinusoidal voltage on the supply node （the ground node） is the cause of the minority carrier diffusion for TLU.

Investigation on latch-up susceptibility induced by high-power microwave in complementary metal–oxide–semiconductor inverter

The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency（PRF） is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.

系统共地引发LATCH-UP及应对措施

每一个系统都有自己的VDD、GND,信号都是相对本系统的GND而言。在某些特殊场合,系统间信号传输切换伴随着"共地"的过程,在这样的过程中若两个GND之间的电位不同,就会在两个不同的GND之间发生能量交换。如果两者电位相差很大,这种能量交换所发生的冲击可能会诱发系统中集成电路内部发生LATCH-UP。文中对这种特殊使用场合发生的LATCH-UP现象进行了描述,并通过对这种LATCH-UP现象的实验、分析,提出抑制发生这种LATCH-UP的措施。

Analysis and Countermeasure for Latch-up of CMOS Device in Electronic System Design

Considering the phenomenon of Latch-up in CMOS device,some patterns of manifestation about Latch-up in electronic system are analyzed with three actual circuits,meanwhile the correlative solving methods are also provided. To avoid Latch-up,some general principles are proposed. The analyzing and solving processes derived from practical system design are verified simple and ef-fective in large number of products,and to some extend have general reference value in anti-latch-up design of application systems.

Latch-up测试中负电流的影响和防护

阐述了在Latch-up测试中负电流的产生机理,以及芯片内部寄生双极晶体管对负电流的连锁反应机理,并以模拟电压缓冲器和线性稳压器为例分析了负电流对芯片可能造成的影响,最后提出了一系列在芯片内部可以采取的防护措施。