The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured re...The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured results show different trends.In heavy ion SEU test,the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array.TCAD simulation was performed.TIDinduced degradation in n MOSFETs mainly induced the imprint effect in the SRAM cell,which is consistent with the measured results under the proton environment,but cannot explain the phenomena observed under heavy ion environment.A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.展开更多
胚胎电子细胞的基因循环存储模块在辐射空间容易受到单粒子翻转(SEU)影响,由于缺乏有效的自检手段,严重制约了胚胎电子阵列在深空等辐射环境中的应用。本文设计了一种新型的具有SEU自修复能力的触发器单元,并结合汉明纠错码,设计了一种...胚胎电子细胞的基因循环存储模块在辐射空间容易受到单粒子翻转(SEU)影响,由于缺乏有效的自检手段,严重制约了胚胎电子阵列在深空等辐射环境中的应用。本文设计了一种新型的具有SEU自修复能力的触发器单元,并结合汉明纠错码,设计了一种新型的具有SEU自检和自修复能力的基因循环存储模块,可以在维持胚胎电子细胞阵列正常工作的情况下,实时有效的检测并修复1 bit SEU。以2 bit进位加法器为例,通过仿真实验,验证了胚胎电子细胞的SEU自检和自修复能力。展开更多
Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4...Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset(MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions.In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers(LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of ^(209)Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-toface structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.展开更多
A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event ups...A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.展开更多
Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Si...Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Single-Event Upsets(SEUs).To insure reliable operation of FPGA based systems in a harsh radiation environment,various SEU mitigation techniques have been provided.In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA.The proposed approach combines the fault injection controller with the host FPGA,and therefore the hardware complexity is minimized.All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA.Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.展开更多
An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an intern...An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.展开更多
Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are...Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are obtained under different incident directions of neutrons:front,back and side.It is found that,for both technology nodes,the“worst direction”corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume.The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions.While for multiple-cell upset(MCU)sensitivity,side incidence is the worst direction,with the highest MCU ratio.The largest MCU for the 14 nm FinFET SRAM involves 8 bits.Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.展开更多
Three-dimensional(3 D)TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor(NMOS)transistor or P-channel metal-oxide semiconductor(PMOS)transistor ca...Three-dimensional(3 D)TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor(NMOS)transistor or P-channel metal-oxide semiconductor(PMOS)transistor can mitigate the cross section of single event upset(SEU)in 14-nm complementary metal-oxide semiconductor(CMOS)bulk Fin FET technology.The competition of charge collection between well boundary and sensitive nodes,the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section.Unlike dualinterlock cell(DICE)design,this approach is more effective under heavy ion irradiation of higher LET,in the presence of enough taps to ensure the rapid recovery of well potential.Besides,the feasibility of this method and its effectiveness with feature size scaling down are discussed.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.U1532261)
文摘The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured results show different trends.In heavy ion SEU test,the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array.TCAD simulation was performed.TIDinduced degradation in n MOSFETs mainly induced the imprint effect in the SRAM cell,which is consistent with the measured results under the proton environment,but cannot explain the phenomena observed under heavy ion environment.A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.
文摘胚胎电子细胞的基因循环存储模块在辐射空间容易受到单粒子翻转(SEU)影响,由于缺乏有效的自检手段,严重制约了胚胎电子阵列在深空等辐射环境中的应用。本文设计了一种新型的具有SEU自修复能力的触发器单元,并结合汉明纠错码,设计了一种新型的具有SEU自检和自修复能力的基因循环存储模块,可以在维持胚胎电子细胞阵列正常工作的情况下,实时有效的检测并修复1 bit SEU。以2 bit进位加法器为例,通过仿真实验,验证了胚胎电子细胞的SEU自检和自修复能力。
基金supported by the Fundamental Research Funds for the Central Universities(No.HIT.KISTP.201404)Harbin science and innovation research special fund(No.2015RAXXJ003)Special fund for development of Shenzhen strategic emerging industries(No.JCYJ20150625142543456)
文摘Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset(MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions.In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers(LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of ^(209)Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-toface structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.
基金the National Natural Science Foundation of China(Nos.12035019,11690041,and 11805244).
文摘A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.
文摘Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Single-Event Upsets(SEUs).To insure reliable operation of FPGA based systems in a harsh radiation environment,various SEU mitigation techniques have been provided.In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA.The proposed approach combines the fault injection controller with the host FPGA,and therefore the hardware complexity is minimized.All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA.Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.
基金Supported by the National High Technology and Development Program of China(2013AA1548)
文摘An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.
基金Project supported by the Key-Area Research and Development Program of Guangdong Province,China(Grant No.2019B010145001)the National Natural Science Foundation of China(Grant Nos.12075065 and 12175045)the Applied Fundamental Research Project of Guangzhou City,China(Grant No.202002030299)
文摘Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are obtained under different incident directions of neutrons:front,back and side.It is found that,for both technology nodes,the“worst direction”corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume.The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions.While for multiple-cell upset(MCU)sensitivity,side incidence is the worst direction,with the highest MCU ratio.The largest MCU for the 14 nm FinFET SRAM involves 8 bits.Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.12035019,11690041,and 62004221)。
文摘Three-dimensional(3 D)TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor(NMOS)transistor or P-channel metal-oxide semiconductor(PMOS)transistor can mitigate the cross section of single event upset(SEU)in 14-nm complementary metal-oxide semiconductor(CMOS)bulk Fin FET technology.The competition of charge collection between well boundary and sensitive nodes,the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section.Unlike dualinterlock cell(DICE)design,this approach is more effective under heavy ion irradiation of higher LET,in the presence of enough taps to ensure the rapid recovery of well potential.Besides,the feasibility of this method and its effectiveness with feature size scaling down are discussed.
