为满足5.8 GHz雷达系统的需要,在HLMC55LP工艺中设计了一款12 bit SAR ADC,ADC的采样率为500 kHz/250 kHz两档可调,采用单调电容开关时序,且在电容阵列的高位部分加上2个冗余位设计,该冗余位对高位的CDAC建立误差,比较器误差都有一定的...为满足5.8 GHz雷达系统的需要,在HLMC55LP工艺中设计了一款12 bit SAR ADC,ADC的采样率为500 kHz/250 kHz两档可调,采用单调电容开关时序,且在电容阵列的高位部分加上2个冗余位设计,该冗余位对高位的CDAC建立误差,比较器误差都有一定的容忍能力,可以带来ADC性能上的提升。系统采用上极板采样,可以在采样周期结束的瞬间就开始逐位比较过程,省去了采用底极板采样第一拍CDAC建立的过程,提高了转换速度,相对于底极板采样也节省了一定的开关功耗。后仿结果表明,模拟输入20 kHz差分中频信号,在500 kHz采样频率,3.3 V电源电压下,ADC的有效位数为11.56 bit,SNR为71.04 dB,SFDR为80.37 dBc,功耗约为2 mW。展开更多
Based on mirror-blocks, a totally coded algorithm (TCA) for switched-current (SI) network analysis in frequency domain is presented. The algorithm is simple, available, and suitable for any swltched-current networ...Based on mirror-blocks, a totally coded algorithm (TCA) for switched-current (SI) network analysis in frequency domain is presented. The algorithm is simple, available, and suitable for any swltched-current networks. A basis of analysis and design for switched-current networks via this algorithm is provided.展开更多
文摘Based on mirror-blocks, a totally coded algorithm (TCA) for switched-current (SI) network analysis in frequency domain is presented. The algorithm is simple, available, and suitable for any swltched-current networks. A basis of analysis and design for switched-current networks via this algorithm is provided.