Comparison of performance between bipolar and unipolar double-frequency sinusoidal pulse width modulation in a digitally controlled H-bridge inverter system

By deriving the discrete-time models of a digitally controlled H-bridge inverter system modulated by bipolar sinu- soidal pulse width modulation （BSPWM） and unipolar double-frequency sinusoidal pulse width modulation （UDFSPWM） respectively, the performances of the two modulation strategies are analyzed in detail. The circuit parameters, used in this paper, are fixed. When the systems, modulated by BSPWM and UDFSPWM, have the same switching frequency, the stabil- ity boundaries of the two systems are the same. However, when the equivalent switching frequencies of the two systems are the same, the BSPWM modulated system is more stable than the UDFSPWM modulated system. In addition, a convenient method of establishing the discrete-time model of piecewise smooth system is presented. Finally, the analytical results are confirmed by circuit simulations and experimental measurements.

Implementation of FPGA Based Hybrid Power Generator for PV and Wind Grid Applications

This paper deals with implementation of Sinusoidal Pulse-Width-Modulation (SPWM) for a single-phase hybrid power filter generator for Photovoltaic (PV) and wind grid applications. Using policy iteration algorithm, an improved variable step-size perturbation and observation algorithm is contrived and it is implemented proficiently using a hard-ware description language (VHDL) (Very High Speed Integrated Circuit Hardware Description Language). Subsequently, the new generated grid source supplements the existing grid power in rural houses during its cut off or restricted supply period. The software is used for generating SPWM modulation integrated with a solar-power & wind power grid system which is implemented on the Spartan 3 FPGA. The proposed algorithm performs as a conventional controller in terms of tracking speed and mitigating fluctuation output power in steady state operation which is shown in the experimental results with a commercial PV array and HPW (Height Weight Proportional) show. Simulation results demonstrate the validity with load of the proposed algorithm.

Reduction of THD in Thirteen-Level Hybrid PV Inverter with Less Number of Switches

Multilevel inverter (MLI) is one of the most efficient power converters which are especially suited for high power applications with reduced harmonics. MLI not only achieves high output power and is also used in renewable energy sources such as photovoltaic, wind and fuel cells. Among various topologies of MLI, this paper mainly focuses on cascaded MLI with three unequal DC sources called asymmetric cascaded MLI which reduces the number of power switches. Various modulation techniques are also reviewed in literature [1]. In this paper we focus on sinusoidal (or) multicarrier pulse width modulation (SPWM) which improves the output voltage at lower modulation index for obtaining lower Total Harmonic Distortion (THD) level. The gating signal for the 13-level hybrid inverter using SPWM technique is generated using Field Programmable Gate Array (FPGA) processor. The proposed modulation technique results in reduced percentage of THD, but lower order harmonics are not eliminated. So a new technique called Selective Harmonic Elimination (SHE) is also implemented in order to reduce the lower order harmonics. The optimum switching angles are determined for obtaining minimum THD. The performance evaluation of the proposed PWM inverter is verified using an experimental model of 13-level cascaded hybrid MLI and compared with MATLAB/SIMULINK model.

High-Precision Dead-Time Intellectual Property Core and Its Compensation for Inverters

In the inverter circuit,there exists a specific on-off time in each power transistor.As such,to prevent a short circuit of the two switch devices on the upper and lower bridge arms,a specific dead time must be set in the pulse width modulation(PWM)and the sinusoidal pulse width modulation(SPWM)signals.In this paper,an intellectual property(IP)core that can introduce a high-precision dead time of arbitrary length into PWM or SPWM signals of the inverter is designed to increase the precision,convenience and generalization of dead time control,resulting in a boosted control accuracy of up to 10 ns.Moreover,the added Avalon bus enables IP cores to be accessed by the field programmable gate array(FPGA)processor in a standard manner and multiple IP cores of the same class can be easily incorporated.In addition,an application for setting and compensating for dead time in a three-phase inverter based on system on programmable chip(SOPC)technology is presented.With the Nios II CPU as its core,the system adopts the mean voltage compensation method to calculate the compensation voltage,and performs dead-time compensation in a feed-forward manner.The three dead-time IP cores are controlled by Avalon bus.These allow the dead time of three groups of power transistors to be accurately controlled and flexibly adjusted.The system also features the master computer communication function while boasting the advantages of flexible control,high precision and low cost.