An Adaptive Slope Compensation Circuit for Peak Current Mode of Boost Switching Power Supply

Based on the analysis of the basic principle of slope compensation, a high-precision adaptive slope compensation circuit for peak current mode boost DC/DC converter is designed. The circuit dynamically detects the input and output voltage of the boost circuit to realize automatic adjustment of the compensation amount with the change of duty ratio, which makes the ramp compensation slope optimized. The design uses a high-precision subtracter to improve the accuracy of slope compensation. While eliminating sub-slope oscillation and improving the stability of boost circuit, the negative impact of compensation on boost circuit is minimized, and the load capacity and transient response speed of boost circuit are guaranteed. The circuit is designed based on SMIC 0.18um CMOS technology, with simple structure, high reliability and easy engineering implementation. Spectre circuit simulator 17.1.0.124 64b simulation results show that the circuit has high compensation accuracy and wide input and output voltage range. When the working voltage is 3.3 V, the compensation slope can be adjusted adaptively under different duty cycles, and the minimum error between the compensation slope and the theoretical optimal compensation slope is only 0.42%.

Principle of designing slope compensation in PFC Boost converter

Due to wide input fluctuation with line frequency of 50 Hz, power-factor-correction （PFC） Boost converters tend to exhibit fast-scale instability over time domain. The traditional remedy is to impose slope compensation so as to weaken or eliminate this instability. A theoretical principle on the implementation of slope compensation signal is still lacking. Empirical design will induce over compensation frequently, resulting in a large decrease of power factor. In order to tackle this issue, by constructing the discrete-time iterative map of the PFC Boost converter from the viewpoint of bifurcation control theory of nonlinear systems, consequently, the criterion of critical stability for the PFC circuit can be established. Based on this stability criterion, appropriate design of slope compensation can be achieved. Our work indicates that 3 main circuit parameters （i.e. switching cycle, output reference voltage and inductor） determine the effective amplitude design of the slope compensation signal. The results, validated by a large quantity of analytical and numerical studies, show that appropriate slope compensation can be effective in weakening （or controlling） fast-scale bifurcation while maintaining a rather high input power factor.

A wide load range,multi-mode synchronous buck DC-DC converter with a dynamic mode controller and adaptive slope compensation

A synchronous buck DC-DC converter with an adaptive multi-mode controller is proposed.In order to achieve high efficiency over its entire load range,pulse-width modulation（PWM）,pulse-skip modulation（PSM） and pulse-frequency modulation（PFM） modes were integrated in the proposed DC-DC converter.With a highly accurate current sensor and a dynamic mode controller on chip,the converter can dynamically change among PWM, PSM and PFM control according to the load requirements.In addition,to avoid power device damage caused by inrush current at the start up state,a soft-start circuit is presented to suppress the inrush current.Furthermore,an adaptive slope compensation（SC） technique is proposed to stabilize the current programmed PWM controller for duty cycle passes over 50%,and improve the degraded load capability due to traditional slope compensation.The buck converter chip was simulated and manufactured under a 0.35μm standard CMOS process.Experimental results show that the chip can achieve 79%to 91%efficiency over the load range of 0.1 to 1000 mA.

Design and implementation of adaptive slope compensation in current mode DC-DC converter

To improve the compensation for the inherent instability in a current mode converter, the adaptive slope compensation, giving attention to the problems of the traditional compensation on compensation accuracy, loading capability and turning jitter, is presented. Based on the analysis of current loop, by detecting the input and output voltage, converting the adaptive slope compensation current, the compensation of the current loop is optimized successfully. It can not only improve the compensation accuracy but also eliminate the over compensation, the turning jitter and the poor loading capability in the reported slope compensation. A power supply chip with adaptive slope compensation has been fabricated in a 0.35 μm CMOS process. The measurement results show that the chip starts up and operates steadily with the constant current limit under conditions of 5 V input voltage, from 10% to 100% duty cycle.

Digital close loop control system for current-programmed mode arc welding inverter

A small-signal model of current programmed mode pulse width modulation converter including the equivalent sampling effect is introduced and analyzed. In this model, an addition pole is brought out by the sampling effect in the current loop gain, and it affects dynamic bandwidth and stability of the inner current loop. By selecting the appropriate stability parameter which determines the additional pole and describes the degree of peaking in closed loop transfer function, a control model of current programmed full bridge arc welding inverter with maximum frequency bandwidth and stability can be obtained. Small and large amplitude pulse current outputs are employed in simulations and experiments and results validate the design method.

A Novel Multi-Channel Dispersion Slope Compensator Using Sampled FBG

A novel dispersion slope compensator is proposed and fabricated using a sampled fiber grating. The dispersion slope of this compensator is demonstrated to match that of Coming LS fiber for a multi-channel 50GHz WDM system.

High performance white LED driver with single-wire serial-pulse digital dimming

A high performance white light emitter diode （LED） driver based on boost converter with novel single-wire serial-pulse digital dimming （SWSP） is proposed. The driver uses external serial programmed pulses and internal clock to simplify brightness control By embedding a 5-bit digital analog converter （DAC） into the driver, wide dimming range is achieved. Moreover, a new dynamic slope compensation circuit is presented and other key circuits of the driver are optimized to get higher efficiency and fast transition response. A practical circuit is implemented with 0.6 um bipolar complementary-metal-oxide-semiconductor double-diffused-metal-oxide-semiconductor （BCD） technology. The simulation results show that the driver can provide both wide output current from 1.3 mA to 42 mA with 32-level digital dimming and higher efficiency up to 83% while it works at 1 MHz switching frequency with the input voltage variation from 2.7 V to 5.5 V.

SAR-GMTI investigation in hybrid along-and cross-track baseline InSAR

A joint-pixel clutter suppression method based on slope compensation is proposed in this paper, In order to eliminate the effect of the terrain interferometric phase caused by the cross-track baseline in hybrid baseline InSAR, the local independent identical distribution of the clutter is satisfied by using the slope compensation technique, and thus the clutter can be suppressed successfully by using the orthogonality of the clutter subspace and the noise subspace. This approach utilizes the information contained in the current pixel as well as in its neighbors, showing robustness to the image coregistration errors. Both the simulated data and the real airborne data are used in proving the validity of the presented approach.