DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

THE NEW SUPER-HIGH-SPEED DIGITAL CIRCUIT BASED ON LINEAR AND-OR GATES

The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.

Designing a Full Adder Circuit Based on Quasi-Floating Gate

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.

Geometric Phase Gate Based on Both Displacement Operator and Squeezed Operators with a Superconducting Circuit Quantum Electrdynamics

We give the brief review on the related definition of the geometric phase independent of specific physical system based on the displacement opreator and the sqeezed operator, then show how the displacement operator and the squeezed operator can induce the general geometric phase. By means of the displacement operator and the squeezed operator concerning the circuit cavity mode state along a closed path in the phase space, we discuss specifically how to implement a two-qubit geometric phase gate in circuit quantum electrodynamics with both single photon interaction and two-photon interaction between the superconducting qubits and the circuit cavity modes. The experimental feasibility is discussed in detail.

Shortcut-based quantum gates on superconducting qubits in circuit QED

Construction of optimal gate operations is significant for quantum computation.Here an efficient scheme is proposed for performing shortcut-based quantum gates on superconducting qubits in circuit quantum electrodynamics(QED).Two four-level artificial atoms of Cooper-pair box circuits,having sufficient level anharmonicity,are placed in a common quantized field of circuit QED and are driven by individual classical microwaves.Without the effect of cross resonance,one-qubit NOT gate and phase gate in a decoupled atom can be implemented using the invariant-based shortcuts to adiabaticity.With the assistance of cavity bus,a one-step SWAP gate can be obtained within a composite qubit-photon-qubit system by inversely engineering the classical drivings.We further consider the gate realizations by adjusting the microwave fields.With the accessible decoherence rates,the shortcut-based gates have high fidelities.The present strategy could offer a promising route towards fast and robust quantum computation with superconducting circuits experimentally.

Simple Scheme for Realizing the General Conditional Phase Shift Gate and a Simulation of Quantum Fourier Transform in Circuit QED

We propose a theoretical scheme for realizing the general conditional phase shift gate of charge qubits situated in a high-Q superconducting transmission line resonator. The phase shifting angle can be tuned from 0 to 27r by simply adjusting the qubit-resonator detuning and the interaction time. Based on this gate proposal, we give a detailed procedure to implement the three-qubit quantum Fourier transform with circuit quantum eleetrodynamics （QED）. A careful analysis of the decoherence sources shows that the algorithm can be achieved with a high fidelity using current circuit QED techniques.

Correction of microwave pulse reflection by digital filters in superconducting quantum circuits

Reducing the control error is vital for high-fidelity digital and analog quantum operations.In superconducting circuits,one disagreeable error arises from the reflection of microwave signals due to impedance mismatch in the control chain.Here,we demonstrate a reflection cancelation method when considering that there are two reflection nodes on the control line.We propose to generate the pre-distortion pulse by passing the envelopes of the microwave signal through digital filters,which enables real-time reflection correction when integrated into the field-programmable gate array(FPGA).We achieve a reduction of single-qubit gate infidelity from 0.67%to 0.11%after eliminating microwave reflection.Real-time correction of microwave reflection paves the way for precise control and manipulation of the qubit state and would ultimately enhance the performance of algorithms and simulations executed on quantum processors.

Remote entangling gate between a quantum dot spin and a transmon qubit mediated by microwave photons

Spin qubits and superconducting qubits are promising candidates for realizing solid-state quantum information processors.Designing a hybrid architecture that combines the advantages of different qubits on the same chip is a highly desirable but challenging goal.Here we propose a hybrid architecture that utilizes a high-impedance SQUID array resonator as a quantum bus,thereby coherently coupling different solid-state qubits.We employ a resonant exchange spin qubit hosted in a triple quantum dot and a superconducting transmon qubit.Since this hybrid system is highly tunable,it can operate in a dispersive regime,where the interaction between the different qubits is mediated by virtual photons.By utilizing such interactions,entangling gate operations between different qubits can be realized in a short time of 30 ns with a fidelity of up to 96.5%under realistic parameter conditions.Further utilizing this interaction,remote entangled state between different qubits can be prepared and is robust to perturbations of various parameters.These results pave the way for exploring efficient fault-tolerant quantum computation on hybrid quantum architecture platforms.

基于载流子抽取模型的Trench Gate/Field-stop IGBT驱动器有源箝位功能分析

针对Trench gate/Field-stop IGBT结构特有的关断过程中集电极电流下降率不可控问题,引入了载流子抽取模型来模拟器件关断过程中的集电极电流下降阶段器件内部载流子的动态行为特性,并以此为基础分析了驱动器为适应Trench gate/Field-Stop IGBT结构这种关断特性而引入的有源箝位功能的作用机理,验证了载流子抽取模型在器件级与电路级交互作用分析中的实用性,为后续实现器件与电路的最佳匹配奠定了基础。

图腾柱式IGBT栅极驱动电路设计

由晶体管BJT构成的图腾柱式栅极驱动电路在单相交错式PFC中被大量应用,本文分析了IGBT栅极特性和栅极驱动电路结构,分别推导了栅极最大电流、 BJT基极电流以及驱动功率的计算方法,全面地得出了IGBT栅极驱动电路关键器件的参数选型和注意事项。

一种应用于NB-IoT通信的高线性CMOS功率放大器

为满足复杂的NB-IoT通信调制模式对功率放大器输出线性度的要求,提出一种面向NB-IoT通信应用的700~900 MHz高线性度CMOS功率放大器(PA)。该放大器采用两级结构,工作于AB类放大状态,驱动级和输出功率级分别采用自偏置的共源共栅结构和共源放大器结构,驱动级为功率级提供大的电压输出摆幅。为提高线性度,采用二极管线性化偏置技术改善晶体管输入电容的非线性导致的增益压缩和相位失真现象,将输出1 dB压缩点提升3.2 dB。采用65 nm/1.2 V CMOS工艺完成电路版图设计,整体放大器的版图尺寸为0.68 mm×1 mm。仿真结果表明,在700~900 MHz工作频带内,功率放大器的小信号增益大于19 dB,输入反射系数S11小于等于-12 dB,功率附加效率(PAE)峰值为29.6%,输出1 dB压缩点为22.7 dBm。所提出的功率放大器电路具有高线性度、低功耗、小尺寸的特点,可有效满足NB-IoT通信并用于700~900 MHz频段内射频信号功率放大的应用需求。

基于FPGA的电能表通信可靠性测试系统

在电网运行过程中,确保电能表数据通信的高度可靠性,对保障电表计量的精准性和电网的稳定运行至关重要。文章设计并实现了基于现场可编程门阵列(Field Programmable Gate Array,FPGA)的电能表通信可靠性测试系统,通过模拟仿真内部集成电路(Inter-Integrated Circuit,I2C)接口,代替真实的I2C接口模块与电能表微控制单元(Micro Controller Unit,MCU)相连。上位机生成并发送测试指令,FPGA芯片承担指令传递的任务,并把电能表MCU返回的数据传送回上位机进行分析处理。该方法解决了电能表通信可靠性测试领域中I2C接口在故障注入、通信帧监听以及多设备连接测试方面灵活性不足等问题。

Design and realization of synchronization circuit for GPS software receiver based on FPGA

With research on the carrier phase synchronization and symbol synchronization algorithm of demodulation module, a synchronization circuit system is designed for GPS software receiver based on field programmable gate array （FPGA）, and a series of experiment is done on the hardware platform. The result shows the all-digital synchronization and demodulation of GPS intermediate frequency （IF） signal can be realized and applied in embedded real-time GPS software receiver system. It is verified that the decision-directed joint tracking algorithm of carrier phase and symbol timing for received signals from GPS is reasonable. In addition, the loop works steadily and can be used for receiving GPS signals using synchronous demodulation. The synchronization circuit for GPS software receiver designed based on FPGA has the features of low cost, miniaturization, low power and real-time. Surely, it will become one of the development directions for GPS and even GNSS embedded real-time software receiver.

Principle and architecture of parallel reconfiguration circuit for ternary optical computer

Reconfiguration is the key to produce an applicable ternary optical computer （TOC）. The method to implement the reconfiguration function determines whether a TOC can step into applied fields or not. In this work, a design of the reconfiguration circuit based on field programmable gates array （FPGA） is proposed, and the structure of the entire hardware system is discussed.

High performance integrated photonic circuit based on inverse design method

The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits.

New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits

New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

Optimized Implementation for Wave Digital Filter Based Circuit Emulation on FPGA

A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.

An Extended Approach for Generating Unitary Matrices for Quantum Circuits

In this paper,we do research on generating unitary matrices for quantum circuits automatically.We consider that quantum circuits are divided into six types,and the unitary operator expressions for each type are offered.Based on this,we propose an algorithm for computing the circuit unitary matrices in detail.Then,for quantum logic circuits composed of quantum logic gates,a faster method to compute unitary matrices of quantum circuits with truth table is introduced as a supplement.Finally,we apply the proposed algorithm to different reversible benchmark circuits based on NCT library(including NOT gate,Controlled-NOT gate,Toffoli gate)and generalized Toffoli(GT)library and provide our experimental results.

Realization of Quantum Circuits in Fock Space

In this letter, by using the method we offered in our paper [L. Ma and Y.D. Zhang, Commun. Theor. Phys.(Beijing, China) 36 (2001) 119], some extended quantum logic gates, such as quantum counter, quantum adder, are studied and their expressions are given. It may be useful for us to study the more complicated quantum logic circuits deeply.