Direct measurement of an energy-dependent single-event-upset cross-section with time-of-flight method at CSNS

To predict the soft error rate for applications, it is essential to study the energy dependence of the single-event-upset(SEU) cross-section. In this work, we present a direct measurement of the SEU cross-section with the Back-n white neutron source at the China Spallation Neutron Source. The measured cross section is consistent with the soft error data from the manufacturer and the result suggests that the threshold energy of the SEU is about 0.5 Me V, which confirms the statement in Iwashita’s report that the threshold energy for neutron soft error is much below that of the(n, α) cross-section of silicon.In addition, an index of the effective neutron energy is suggested to characterize the similarity between a spallation neutron beam and the standard atmospheric neutron environment.

Soft error reliability in advanced CMOS technologies—trends and challenges

With the decrease of the device size,soft error induced by various particles becomes a serious problem for advanced CMOS technologies.In this paper,we review the evolution of two main aspects of soft error-SEU and SET,including the new mechanisms to induced SEUs,the advances of the MCUs and some newly observed phenomena of the SETs.The mechanisms and the trends with downscaling of these issues are briefly discussed.We also review the hardening strategies for different types of soft errors from different perspective and present the challenges in testing,modeling and hardening assurance of soft error issues we have to address in the future.

Mechanisms of atmospheric neutron-induced single event upsets in nanometric SOI and bulk SRAM devices based on experiment-verified simulation tool

In this paper, a simulation tool named the neutron-induced single event effect predictive platform（NSEEP^2） is proposed to reveal the mechanism of atmospheric neutron-induced single event effect（SEE） in an electronic device, based on heavy-ion data and Monte-Carlo neutron transport simulation. The detailed metallization architecture and sensitive volume topology of a nanometric static random access memory（SRAM） device can be considered to calculate the real-time soft error rate（RTSER） in the applied environment accurately. The validity of this tool is verified by real-time experimental results. In addition, based on the NSEEP^2, RTSERs of 90 nm–32 nm silicon on insulator（SOI） and bulk SRAM device under various ambient conditions are predicted and analyzed to evaluate the neutron SEE sensitivity and reveal the underlying mechanism. It is found that as the feature size shrinks, the change trends of neutron SEE sensitivity of bulk and SOI technologies are opposite, which can be attributed to the different MBU performances. The RTSER of bulk technology is always 2.8–64 times higher than that of SOI technology, depending on the technology node, solar activity, and flight height.

PIPBQ Effect Aware SER Analysis for Combinational Logic Circuits

Technology scaling results in the propagation-induced pulse broadening and quenching（PIPBQ） effect become more noticeable.In order to effectively evaluate the soft error rate for combinational logic circuits,a soft error rate analysis approach considering the PIPBQ effect is proposed.As different original pulse propagating through logic gate cells,pulse broadening and quenching are measured by HSPICE.After that,electrical effect look-up tables（EELUTs） for logic gate cells are created to evaluate the PIPBQ effect.Sensitized paths are accurately retrieved by the proposed re-convergence aware sensitized path search algorithm.Further,by propagating pulses on these paths to simulate fault injection,the PIPBQ effect on these paths can be quantified by EELUTs.As a result,the soft error rate of circuits can be effectively computed by the proposed technique.Simulation results verify the soft error rate improvement comparing with the PIPBQ-not-aware method.

Implementation and Analysis of Probabilistic Methods for Gate-Level Circuit Reliability Estimation

The development of VLSI technology results in the dramatically improvement of the performance of integrated circuits. However, it brings more challenges to the aspect of reliability. Integrated circuits become more susceptible to soft errors. Therefore, it is imperative to study the reliability of circuits under the soft error. This paper implements three probabilistic methods (two pass, error propagation probability, and probabilistic transfer matrix) for estimating gate-level circuit reliability on PC. The functions and performance of these methods are compared by experiments using ISCAS85 and 74-series circuits.