Prevention from Soft Errors via Architecture Elasticity

Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures h01istically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.

Timing Error Aware Register Allocation in TS

Timing speculative(TS)architecture is promising for improving the energy efficiency of microprocessors.Error recovery units,designed for tolerating occasional timing errors,have been used to support a wider range of voltage scaling,therefore to achieve a better energy efficiency.More specifically,the timing error rate,influenced mainly by data forwarding,is the bottleneck for voltage down-scaling in TS processors.In this paper,a new Timing Error Aware Register Allocation method is proposed.First,we designed the Dependency aware Interference Graph(DIG)construction to get the information of Read after Write(RAW)in programs.To build the construction,we get the disassemble code as input and suppose that there are unlimited registers,the same way as so-called virtual registers in many compilers.Then we change the disassemble codes to the SSA form for each basic block to make sure the registers are defined only once.Based on the DIG construction,registers were real-located to eliminate the timing error,by loosening the RAW dependencies.We con-struct the DIG for each function of the program and sort the edge of DIG by an increasing weight order.Since a smaller weighted-edge value means that its owner nodes have more frequent access in instruction flows,we expect it in different registers with no read-write dependency.At the same time,we make sure that there are no additional new spill codes emerging in our algorithm to minimize the rate of spill code.A high rate of spill code will not only decrease the performance of the system but also increase the unexpected read-write dependency.Next,we reallocate the reg-isters by weight order in turn to loosen the RAW dependencies.Furthermore,we use the NOP operation to pad the instructions with a minimal distance value of 2.Experiment results showed that the average distance of RAW dependencies was increased by over 20%.