Proposal for sequential Stern-Gerlach experiment with programmable quantum processors

The historical significance of the Stern–Gerlach(SG)experiment lies in its provision of the initial evidence for space quantization.Over time,its sequential form has evolved into an elegant paradigm that effectively illustrates the fundamental principles of quantum theory.To date,the practical implementation of the sequential SG experiment has not been fully achieved.In this study,we demonstrate the capability of programmable quantum processors to simulate the sequential SG experiment.The specific parametric shallow quantum circuits,which are suitable for the limitations of current noisy quantum hardware,are given to replicate the functionality of SG devices with the ability to perform measurements in different directions.Surprisingly,it has been demonstrated that Wigner’s SG interferometer can be readily implemented in our sequential quantum circuit.With the utilization of the identical circuits,it is also feasible to implement Wheeler’s delayed-choice experiment.We propose the utilization of cross-shaped programmable quantum processors to showcase sequential experiments,and the simulation results demonstrate a strong alignment with theoretical predictions.With the rapid advancement of cloud-based quantum computing,such as BAQIS Quafu,it is our belief that the proposed solution is well-suited for deployment on the cloud,allowing for public accessibility.Our findings not only expand the potential applications of quantum computers,but also contribute to a deeper comprehension of the fundamental principles underlying quantum theory.

Efficient cache replacement framework based on access hotness for spacecraft processors

A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity of contemporary high-performance spacecraft processors.To harness these non-uniform access behaviors,an efficient cache replacement framework featuring an auxiliary cache specifically designed to retain evicted hot data was proposed.This framework reconstructs the cache replacement policy,facilitating data migration between the main cache and the auxiliary cache.Unlike traditional cacheline-granularity policies,the approach excels at identifying and evicting infrequently used data,thereby optimizing cache utilization.The evaluation shows impressive performance improvement,especially on workloads with irregular access patterns.Benefiting from fine granularity,the proposal achieves superior storage efficiency compared with commonly used cache management schemes,providing a potential optimization opportunity for modern resource-constrained processors,such as spacecraft processors.Furthermore,the framework complements existing modern cache replacement policies and can be seamlessly integrated with minimal modifications,enhancing their overall efficacy.

THE DESIGN AND IMPLEMENTATION OF THE IEEE 802.11 MAC BASED ON SOFT-CORE PROCESSOR AND RTOS

The implementation method of the IEEE 802.11 Medium Access Control (MAC) protocol is mainly based on DSP (Digital Signal Processor)/ ARM (Advanced Reduced instruction set computer Machine) processor or DSP/ARM IP (Intellectual Property) core. This paper presents a method based on Nios II soft-core processor embedded in Altera’s Cyclone FPGA (Field Programmable Gate Array) and MicroC/OS-II RTOS (Real-Time Operation System). The benefits and drawbacks of above methods are compared, and then the method presented in this paper is described. The hardware and software partitioning are discussed; the hardware architecture is also illustrated and the MAC software programming is described in detail. The presented method has some advantages, such as low cost, easy-implementation and very suitable for the implementation of IEEE 802.11 MAC in research stage.

Speeding up the MATLAB complex networks package using graphic processors

The availability of computers and communication networks allows us to gather and analyse data on a far larger scale than previously. At present, it is believed that statistics is a suitable method to analyse networks with millions, or more, of vertices. The MATLAB language, with its mass of statistical functions, is a good choice to rapidly realize an algorithm prototype of complex networks. The performance of the MATLAB codes can be further improved by using graphic processor units （GPU）. This paper presents the strategies and performance of the GPU implementation of a complex networks package, and the Jacket toolbox of MATLAB is used. Compared with some commercially available CPU implementations, GPU can achieve a speedup of, on average, 11.3x. The experimental result proves that the GPU platform combined with the MATLAB language is a good combination for complex network research.

SDN-Based Switch Implementation on Network Processors

Virtualization is the key technology of cloud computing. Network virtualization plays an important role in this field. Its performance is very relevant to network virtualizing. Nowadays its implementations are mainly based on the idea of Software Define Network (SDN). Open vSwitch is a sort of software virtual switch, which conforms to the OpenFlow protocol standard. It is basically deployed in the Linux kernel hypervisor. This leads to its performance relatively poor because of the limited system resource. In turn, the packet process throughput is very low.In this paper, we present a Cavium-based Open vSwitch implementation. The Cavium platform features with multi cores and couples of hard ac-celerators. It supports zero-copy of packets and handles packet more quickly. We also carry some experiments on the platform. It indicates that we can use it in the enterprise network or campus network as convergence layer and core layer device.

LOGIC STRUCTURE OF PROGRAMMABLE INSTRUCTIONS FOR JAVA PROCESSORS

There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.

High-Level Portable Programming Language for Optimized Memory Use of Network Processors

Network processors (NPs) are widely used for programmable and high-performance networks;however, the programs for NPs are less portable, the number of NP program developers is small, and the development cost is high. To solve these problems, this paper proposes an open, high-level, and portable programming language called “Phonepl”, which is independent from vendor-specific proprietary hardware and software but can be translated into an NP program with high performance especially in the memory use. A common NP hardware feature is that a whole packet is stored in DRAM, but the header is cached in SRAM. Phonepl has a hardware-independent abstraction of this feature so that it allows programmers mostly unconscious of this hardware feature. To implement the abstraction, four representations of packet data type that cover all the packet operations (including substring, concatenation, input, and output) are introduced. Phonepl have been implemented on Octeon NPs used in plug-ins for a network-virtualization environment called the VNode Infrastructure, and several packet-handling programs were evaluated. As for the evaluation result, the conversion throughput is close to the wire rate, i.e., 10 Gbps, and no packet loss (by cache miss) occurs when the packet size is 256 bytes or larger.

Trends of Communication Processors

Processors have been playing important roles in both communication infrastructure systems and terminals.In this paper,both application specific and general purpose processors for communications are discussed including the roles,the history,the current situations,and the trends.One trend is that ASIPs(Application Specific Instruction-set Processors) are taking over ASICs(Application Specific Integrated Circuits) because of the increasing needs both on performance and compatibility of multi-modes.The trend opened opportunities for researchers crossing the boundary between communications and computer architecture.Another trend is the serverlization,i.e.,more infrastructure equipments are replaced by servers.The trend opened opportunities for researchers working towards high performance computing for communication,such as research on communication algorithm kernels and real time programming methods on servers.

Multi-core optimization for conjugate gradient benchmark on heterogeneous processors

Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.

Energy Efficient Hyperparameter Tuned Deep Neural Network to Improve Accuracy of Near-Threshold Processor

When it comes to decreasing margins and increasing energy effi-ciency in near-threshold and sub-threshold processors,timing error resilience may be viewed as a potentially lucrative alternative to examine.On the other hand,the currently employed approaches have certain restrictions,including high levels of design complexity,severe time constraints on error consolidation and propagation,and uncontaminated architectural registers(ARs).The design of near-threshold circuits,often known as NT circuits,is becoming the approach of choice for the construction of energy-efficient digital circuits.As a result of the exponentially decreased driving current,there was a reduction in performance,which was one of the downsides.Numerous studies have advised the use of NT techniques to chip multiprocessors as a means to preserve outstanding energy efficiency while minimising performance loss.Over the past several years,there has been a clear growth in interest in the development of artificial intelligence hardware with low energy consumption(AI).This has resulted in both large corporations and start-ups producing items that compete on the basis of varying degrees of performance and energy use.This technology’s ultimate goal was to provide levels of efficiency and performance that could not be achieved with graphics processing units or general-purpose CPUs.To achieve this objective,the technology was created to integrate several processing units into a single chip.To accomplish this purpose,the hardware was designed with a number of unique properties.In this study,an Energy Effi-cient Hyperparameter Tuned Deep Neural Network(EEHPT-DNN)model for Variation-Tolerant Near-Threshold Processor was developed.In order to improve the energy efficiency of artificial intelligence(AI),the EEHPT-DNN model employs several AI techniques.The notion focuses mostly on the repercussions of embedded technologies positioned at the network’s edge.The presented model employs a deep stacked sparse autoencoder(DSSAE)model with the objective of creating a variation-tolerant NT processor.The time-consuming method of modifying hyperparameters through trial and error is substituted with the marine predators optimization algorithm(MPO).This method is utilised to modify the hyperparameters associated with the DSSAE model.To validate that the proposed EEHPT-DNN model has a higher degree of functionality,a full simulation study is conducted,and the results are analysed from a variety of perspectives.This was completed so that the enhanced performance could be evaluated and analysed.According to the results of the study that compared numerous DL models,the EEHPT-DNN model performed significantly better than the other models.

Processors处理器

2003年里，我们在处理器市场上看到了一幕幕重头戏的上演,基于Hyper Threading技术的Pentium4处理器、Pentium 4 EE、AMD Athlon 64、AMD Athlon 64FX系列，这些新产品的快速推出让人有目不暇接的感觉。

Controller Design for Induction and Brushless Motors Using Matlab with Digital Signal Processor (DSP)

The automation process is a very important pillar for Industry 4.0.One of the first steps is the control of motors to improve production efficiency and generate energy savings.In mass production industries,techniques such as digital signal processing(DSP)systems are implemented to control motors.These systems are efficient but very expensive for certain applications.From this arises the need for a controller capable of handling AC and DC motors that improves efficiency and maintains low energy consumption.This project presents the design of an adaptive control system for brushless AC induction and DC motors,which is functional to any type of plant in the industry.The design was possible by implementing Matlab software and tools such as digital signal processor(DSP)and Simulink.Through an extensive investigation of the state of the art,three models needed to represent the control system have been specified.The first model for the AC motor,the second for the DC motor and the third for the DSP control;this is done in this way so that the probability of failure is lower.Subsequently,these models have been programmed in Simulink,integrating the three main models into one.In this way,the design of a controller for use in AC induction motors,specifically squirrel cage and brushless DC motors,has been achieved.The final model represents a response time of 0.25 seconds,which is optimal for this type of application,where response times of 2e-3 to 3 seconds are expected.

基于Amdahl定律的异构多核密码处理器能效模型研究

边缘计算安全的资源受限特征及各种新型密码技术的应用,对多核密码处理器的高能效、异构性提出需求,但当前尚缺乏相关的异构多核能效模型研究.本文基于扩展Amdahl定律,引入密码串并特征、异构多核结构、数据准备时间、动态电压频率调节等因素,将核划分空闲、活跃状态,建立异构多核密码处理器的能效模型.MATLAB仿真结果表明,数据准备时间占比小于10%时,对能效的负面影响大幅下降;固定电压,频率缩放会影响能效值大小;处理器核空闲/活跃能耗比例越小,能效值越大.架构上,固定异构核,同构核数量与密码任务最大并行度相等时能效值最大,最佳异构核数可由模型变化参数仿真得到;多任务调度执行上,流水与并发执行有利于能效值的进一步提升.多核密码处理器芯片板级测试结果表明,仿真结果与实测数据相关系数接近1,芯片实测的数据准备时间、电压频率缩放等因素的影响与仿真分析基本一致,验证了所提能效模型的有效性.该文重点从影响能效变化趋势因素上,为多核密码处理器异构、高能效设计提供一定的理论分析基础与建议.

用于单片机实验教学的红外激光气体检测仪

为了实现科研反哺教学、促进教学与科研的深度融合,研制了一种基于嵌入式多核处理器和数字信号处理器的实验教学用红外激光气体检测仪。该检测仪包括光学系统和电学系统,其中电学系统包含光谱信息感知模块和嵌入式控制模块。利用研制的检测仪开展了氨制冷冷库现场的泄漏氨气浓度的检测应用。结果表明,与传统气体检测仪相比,该检测仪实现了检测仪的网络化与智能化,而且性能满足实验教学要求。

电极间隙对脉冲电场处理器杀菌效果的影响

脉冲电场是新型非热杀菌技术,杀菌效率高、有效保留液体食品的营养成分,具有广阔的应用前景。电极间隙作为脉冲电场杀菌处理器的关键指标,决定处理器的电场分布和杀菌效果。为了获得最佳间隙参数,提升杀菌效果,为此设计了共场型脉冲电场处理器,电极间距分别为3、5和7 mm,针对固定电导率(等效鲜榨柚子汁电导率)的2种典型细菌(金黄色葡萄球菌和大肠杆菌)菌悬液,研究了脉冲电场的杀菌效果。研究发现,3 mm电极间距所能施加最大电压为18 kV,5、7 mm的可达30 kV;处理时间为120 s时,3种间隙的杀菌效率均可达99.99%。因此,综合考虑电源性能、设备能耗和处理能力,首选3 mm电极间距为处理器的应用参数。评估外施电压幅值对杀菌效果的影响,发现细菌存活量的下降趋势可根据其下降速率分为“慢-快-慢”3个阶段。结合菌悬液上清液蛋白质含量的上升趋势,充分说明了电穿孔应为脉冲电场的主要杀菌机制。

基于MOMA的可重入混合流水车间调度问题研究

针对可重入制造系统多具有多品种、大规模、混流生产等特点,构建带批处理机的可重入混合流水车间调度问题(reentrant hybrid flow shop scheduling problem with batch processors,BPRHFSP)模型,提出一种改进的多目标蜉蝣算法(multi-objective mayfly algorithm,MOMA)进行求解。提出了单件加工阶段和批处理阶段的解码规则;设计了基于Logistic混沌映射的反向学习初始化策略、改进的蜉蝣交配和变异策略,提高了算法初始解的质量和局部搜索能力;根据编码规则设计了基于变邻域下降搜索的蜉蝣运动策略,优化了种群方向。通过对不同规模大量测试算例的仿真实验,验证了MOMA相比传统算法求解BP-RHFSP更具有效性和优越性。所提出的模型能够反映生产的基础特征,达到减少最大完工时间、机器负载和碳排放的目的。

MVSim:面向VLIW多核向量处理器的快速、可扩展和精确的体系结构模拟器

设计了一个面向VLIW多核向量处理器的快速、可扩展、精确的体系结构模拟器MVSim。设计了可扩展的VLIW多核向量处理器模型、多级存储体系结构模型和多核性能模型;实现了指令集架构的节拍精准模拟,Cache、DMA和多核同步部件的高效功能模拟,采用多线程技术实现了多核处理器的高效和可扩展模拟。实验结果表明,MVSim能够准确模拟多核处理器的目标程序执行,模拟结果完全正确,具有良好的可扩展性。MVSim的平均模拟速度分别是RTL模拟和CCS的227倍和5倍,平均性能误差约为2.9%。

长向量处理器高效RNN推理方法

模型深度的不断增加和处理序列长度的不一致对循环神经网络在不同处理器上的性能优化提出巨大挑战。针对自主研制的长向量处理器FT-M7032,实现了一个高效的循环神经网络加速引擎。该引擎采用行优先矩阵向量乘算法和数据感知的多核并行方式,提高矩阵向量乘的计算效率;采用两级内核融合优化方法降低临时数据传输的开销;采用手写汇编优化多种算子,进一步挖掘长向量处理器的性能潜力。实验表明,长向量处理器循环神经网络推理引擎可获得较高性能,相较于多核ARM CPU以及Intel Golden CPU,类循环神经网络模型长短记忆网络可获得最高62.68倍和3.12倍的性能加速。