With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and...With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.展开更多
利用变量节点符号可靠度在迭代过程中的分布特征,提出了一种基于可靠度差值特征的自适应判决多元低密度奇偶校验(Low Density Parity Check, LDPC)译码算法。整个迭代过程划分为两个阶段,针对不同阶段节点可靠度的差值特征分别采用不同...利用变量节点符号可靠度在迭代过程中的分布特征,提出了一种基于可靠度差值特征的自适应判决多元低密度奇偶校验(Low Density Parity Check, LDPC)译码算法。整个迭代过程划分为两个阶段,针对不同阶段节点可靠度的差值特征分别采用不同的判决策略:前期阶段,采用传统的基于最大可靠度的判决策略;后期阶段,根据最大、次大可靠度之间的差值特征,设计自适应的码元符号判决策略。仿真结果表明,所提算法在相当的译码复杂度前提下,能获得0.15~0.4 dB的性能增益。同时,对于列重较小的LDPC码,具有更低的译码错误平层。展开更多
该文提出一种低复杂度的迭代大数逻辑LDPC译码算法,在迭代过程中所有的译码信息都以二元形式进行传递、处理和迭代更新。所提算法不需要计算外信息,而是利用Tanner图上伴随式的对错状态来评判节点可靠度。与现有的几种迭代大数逻辑译码...该文提出一种低复杂度的迭代大数逻辑LDPC译码算法,在迭代过程中所有的译码信息都以二元形式进行传递、处理和迭代更新。所提算法不需要计算外信息,而是利用Tanner图上伴随式的对错状态来评判节点可靠度。与现有的几种迭代大数逻辑译码算法相比,该文算法也不需要信息修正处理,避免了相应的实数乘法操作,具有很低的译码复杂度。此外,该文引入一种特殊的量化处理函数,并给出了基于离散密度进化的参数优化过程。实验仿真表明,该文所提算法与原算法相比,在AWGN信道下可获得约0.3~0.4 d B的性能提升。同时,由于节点间交换传递的译码信息都是基于1个比特位的二元信息,也非常便于硬件的设计与实现。展开更多
大数逻辑可译低密度奇偶校验(LDPC)码是一类具有较大列重的码,针对此类特殊的LDPC码,提出了一种基于整数可靠度的低复杂度自适应译码算法。在译码的过程中,算法对每个校验节点分别引入不同的自适应修正因子对外信息进行修正。仿真表明...大数逻辑可译低密度奇偶校验(LDPC)码是一类具有较大列重的码,针对此类特殊的LDPC码,提出了一种基于整数可靠度的低复杂度自适应译码算法。在译码的过程中,算法对每个校验节点分别引入不同的自适应修正因子对外信息进行修正。仿真表明提出的自适应译码算法的性能与和积译码算法的性能相当,在误码率(BER)约为10-5时两种算法性能之间仅有0.1 d B的差异。所提算法具有复杂度低、可并行操作、全整数的信息传递等优点,十分有利于工程实现。展开更多
基金supported in part by the NSF of China (61471131, 61771149, 61501126)NSF of Guangdong Province 2016A030310337+1 种基金the open research fund of National Mobile Communications Research Laboratory, Southeast University (No. 2018D02)the Guangdong Province Universities and Colleges Pearl River Scholar Funded Scheme (2017-ZJ022)
文摘With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.
文摘该文提出一种低复杂度的迭代大数逻辑LDPC译码算法,在迭代过程中所有的译码信息都以二元形式进行传递、处理和迭代更新。所提算法不需要计算外信息,而是利用Tanner图上伴随式的对错状态来评判节点可靠度。与现有的几种迭代大数逻辑译码算法相比,该文算法也不需要信息修正处理,避免了相应的实数乘法操作,具有很低的译码复杂度。此外,该文引入一种特殊的量化处理函数,并给出了基于离散密度进化的参数优化过程。实验仿真表明,该文所提算法与原算法相比,在AWGN信道下可获得约0.3~0.4 d B的性能提升。同时,由于节点间交换传递的译码信息都是基于1个比特位的二元信息,也非常便于硬件的设计与实现。
文摘大数逻辑可译低密度奇偶校验(LDPC)码是一类具有较大列重的码,针对此类特殊的LDPC码,提出了一种基于整数可靠度的低复杂度自适应译码算法。在译码的过程中,算法对每个校验节点分别引入不同的自适应修正因子对外信息进行修正。仿真表明提出的自适应译码算法的性能与和积译码算法的性能相当,在误码率(BER)约为10-5时两种算法性能之间仅有0.1 d B的差异。所提算法具有复杂度低、可并行操作、全整数的信息传递等优点,十分有利于工程实现。
