Hardware/software co-verification platform for EOS design

Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.

Scheduling Algorithm Based on Storage Capacity of Communication in Hardware/Software Integrated System

In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.

Hardware/software partitioning based on dynamic combination of maximum entropy and chaos optimization algorithm

This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.

A hardware/software co-optimization approach for embedded software of MP3 decoder

In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture.

The Dynamic Prediction Model of Number of Participants in Software Crowd Sourcing Collaboration Development Project

Many online platforms providing crowd with opportunities to participate in software development projects have been existed for a while. Meanwhile, many enterprises are using crowd source to collaboratively develop their software via these platforms in recent years. However, some software development projects in these platforms hardly attract users to join. Therefore, these project owners need a way to effectively predict the number of participants in their projects and accordingly well plan their software and project specifications, such as the program language and the size of the documentation, in order to attract more individuals to participant in the projects. Compared with the past prediction models, our proposed model can dynamically add the factors, such as number of participants in the initial stage of the project, within the project life cycle and make the adjustment to the prediction model. The proposed model was also verified by using cross validation method. The results show that: 1) The models with the factor “the number of user participation” is more accurate than the model without it. 2) The factors of crowd dimension are more influential on the prediction accuracy than those of software project and owner dimensions. It is suggested that the project owners not only just consider those factors of the software project dimension in the initial stage of the project life cycle but also those factors of crowd and interaction dimensions in the late stage to attract more participants in their projects.

New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns

This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.

TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction

We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction, all in one simulation environment. A specifically innovative feature is the co-emulation of selected nodes at clock-cycle-accurate hardware processing level, allowing code debug and exact execution latency evaluation (considering both protocol stack and application), together with other nodes at abstract protocol level, meeting a designer’s needs of simulation speed, scalability and reliability. The simulator is centered on the Zigbee protocol and can be retargeted for different node micro-architectures.

Maturity assessment model for aircraft collaborative design software solution

In order to assure quality and control process in the development of the aircraft collaborative design software, a maturity assessment model is proposed. The requirements designing—house of quality is designed to evaluate the maturity degree of the solution, and the evaluation results can help to manage and control the development process. Furthermore, a fuzzy evaluation method based on the minimum deviation is proposed to deal with the fuzzy information. The quantitative evaluation result of the maturity degree can be calculated by optimizing the semantic discount factor aim for the minimum deviation. Finally, this model is illustrated and analyzed by an example study of the aircraft collaborative design software.

Towards High-Performance Graph Processing: From a Hardware/Software Co-Design Perspective

Graph processing has been widely used in many scenarios,from scientific computing to artificial intelligence.Graph processing exhibits irregular computational parallelism and random memory accesses,unlike traditional workloads.Therefore,running graph processing workloads on conventional architectures(e.g.,CPUs and GPUs)often shows a significantly low compute-memory ratio with few performance benefits,which can be,in many cases,even slower than a specialized single-thread graph algorithm.While domain-specific hardware designs are essential for graph processing,it is still challenging to transform the hardware capability to performance boost without coupled software codesigns.This article presents a graph processing ecosystem from hardware to software.We start by introducing a series of hardware accelerators as the foundation of this ecosystem.Subsequently,the codesigned parallel graph systems and their distributed techniques are presented to support graph applications.Finally,we introduce our efforts on novel graph applications and hardware architectures.Extensive results show that various graph applications can be efficiently accelerated in this graph processing ecosystem.

Research on Software Radio Fuze

The functions and characteristics of software radio are discussed. Using techniques and method of software radio, the concept and advantages of a new kind of radio fuze, software radio fuze, are analysed. Several kinds of hardware platform structures of the software radio fuze are studied and the key techniques are analysed. The software radio fuze will become the most promising radio fuze techniques in 21st century.

Domain-Oriented Software Defined Computing Architecture

With the introduction of software defined hardware by DARPA Electronics Resurgence Initiative,software definition will be the basic attribute of information system.Benefiting from boundary certainty and algorithm aggregation of domain applications,domain-oriented computing architecture has become the technical direction that considers the high flexibility and efficiency of information system.Aiming at the characteristics of data-intensive computing in different scenarios such as Internet of Things(IoT),big data,artificial intelligence(AI),this paper presents a domain-oriented software defined computing architecture,discusses the hierarchical interconnection structure,hybrid granularity computing element and its computational kernel extraction method,finally proves the flexibility and high efficiency of this architecture by experimental comparison.

The Software Industry Promotes All-round Cooperation

Software can be seen almost everywhere and is now defining the world.Software has transitioned from an affiliate of hardware,to a network service that is present in every corner of our social lives.

System-on-a-Chip (SoC) Based Hardware Acceleration for Video Codec

Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced video coding method, H.264 is introduced to reduce the large video data dramatically (usually by 70X or more). However, computational overhead occurs when coding and decoding H.264 video. In this paper, a System-on-a-Chip (SoC) based hardware acceleration solution for video codec is proposed, which can also be used for other software applications. The characteristics of the video codec are analyzed by using the profiling tool. The Hadamard function, which is the bottleneck of H.264, is identified not only by execution time but also another two attributes, such as cycle per loop and loop round. The Co-processor approach is applied to accelerate the Hadamard function by transforming it to hardware. Performance improvement, resource costs and energy consumption are compared and analyzed. Experimental results indicate that 76.5% energy deduction and 8.09X speedup can be reached after balancing these three key factors.

“I’m Just Guiding You”: An Exploration of Software Design Mentorship within a Software Engineering Firm

The case study presented here uses an interpretivist (qualitative, humanistic) approach to illustrate and describe a range of interactions and behaviors that occur during design meetings where mentoring and design simultaneously occur within a software engineering firm, during a portion of the design phase for a software project. It attempts to examine the interaction between two design team members (one novice and one expert) and describes how these observations intersect with the theoretical and applied literature and actual design processes. Taking cues from two theoretical descriptions of the design process, the study presented here suggests that modes and models of mentorship should be added, when applicable, as a descriptive portion of the design process.

从ware到software

随着电子计算机的日益普及,今天在美国由—ware这个构词成分所组成的词屡屡可见。据美国哈佛大学的教育学教授 Howard Gardner声称,在近期召开的一次有关人工智能的学术会议之后,—ware词突然变得风靡起来。一位长期从事人类记忆研究的神经生物家甚至说,他觉得自已还不能适应这种情况,完全成了“a student of wetware among thecomputer hackers”(处在电子计算机专家中间一名学生)。从80年代初开始,wetware一词便被用来指 human brain。本来也可以用另外几个词:skullware,grayware(gray

Development Methodologies for Network Softwarization: A Comparison of DevOps, NetOps, and Verification

This white paper explores three popular development methodologies for network softwarization: DevOps, NetOps, and Verification. The paper compares and contrasts the strengths and weaknesses of each approach and provides recommendations for organizations looking to adopt network softwarization.

虚拟现实技术在数字媒体交互中的应用

相比于传统媒体技术,数字媒体采用更多的先进技术,是信息量大、操作体验感好、支持用户更多的主动操作。虚拟现实技术可以提供良好的体验感、满意度、实时性,对于数字媒体技术交互过程的改变具有重要的意义。该文首先从硬件角度分析基于虚拟现实技术的数字媒体交互采用的设备,包括计算机设备、头盔、手套、手柄、运动捕捉、模拟驾驶和全息现实等。其次从软件角度分析基于虚拟现实技术的数字媒体交互的设计流程和框架,包括虚拟现实软件平台、模拟和交互软件、内容开发工具等软件环境的支持等。性能测试实验结果显示,基于虚拟现实的数字媒体交互过程设计,最终用户使用满意度达到95%以上,实时性提高12%以上。

油田开发中精细油藏描述成果平台建设研究

精细油藏描述是油田开发最基础的工作之一,历来受到研究者的高度重视。目前精细油藏描述中存在的突出问题主要包括研究成果继承性差、基础资料存储不规范、专业软件需求缺口大、成果应用需加强和成果存储管理不规范等5方面。文章通过精细油藏描述成果平台建设,可以从基础数据的整理准备、专业软件共享和协同研究、成果标准规范化存储管理等方面解决上述问题。精细油藏描述数据管理主要包括项目整体数据信息的统计和分析、项目研究数据的整理和统计、成果平台与其他数据平台的对接和数据调用等。精细油藏描述协同研究过程主要包括专业软件的平台实现和使用、不同专业软件之间中间成果的转换和调用、研究工作的自动化实现和完成。精细油藏描述成果存储和管理主要包括成果上传管理中格式的统一规范、成果存储上传中的质量控制、成果生产应用中的跟踪和更新。

通用信道编译码算法物理性能快速仿真系统

为实现信道编译码硬件算法物理性能的快速、准确验证,提出一种软硬件协同的通用化信道编译码算法物理性能快速仿真与性能评估系统。PC上位机软件主要实现模拟信源/噪声数据生成、仿真数据后分析、数据/控制指令传输以及与FPGA下位机交互等功能;FPGA下位机通过设计数据调度与系统控制、信道编译码算法架构、加噪信道以及数据统计等单元,构建通用编译码算法验证系统硬件系统架构,支持不同信道编译码算法物理性能的高效、准确验证。以系统当前支持的BCH码、LDPC码、删余卷积码、RS码及其串行级联码的性能仿真为例开展性能测试,性能恶化最大值低于0.4 dB,在10-7误码率统计量级下,仿真时间低于12 s,验证仿真评估系统的准确性、可靠性与有效性。系统采用的通用级联架构还可支持其他信道编译码算法的快速移植与部署,可为信道编译码算法物理性能快速验证提供一种有效的解决方案。

能源动力类别研究生产教融合联合培养基地建设模式与实践

培养出满足新时代要求的具有创新精神和实践能力的高水平能源动力类别研究生是我国早日实现“双碳”目标的迫切需求。构建产教融合联合培养基地,是深化产教融合、实现能源动力类别研究生教育高质量发展的关键环节。该文总结长安大学在能源动力类别(动力工程及电气工程)研究生培养中基于产教融合建设联合培养基地的模式及实践工作,提出软-硬件协同构建产教融合联合培养实践基地的理念,具体阐述该理念在动力工程及电气工程等能源动力类别研究生培养中的具体实践与应用,以期为能源动力类别研究生实践创新能力的培养提供参考。