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ESD performance of LDMOS with source-bulk layout structure optimization
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作者 蒋苓利 樊航 +1 位作者 林丽娟 张波 《Journal of Semiconductors》 EI CAS CSCD 2013年第12期40-44,共5页
To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout ... To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vtl is reduced from 55.53 to 50.69 V. 展开更多
关键词 ESD LDMOS source-bulk layout structure
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