Verification of instruction set specification for an ASIP

In order to gain the great performance of ASIP, this paper discusses different aspects of an ASIP instruction set specification like syntax, encoding, constraints as welt as behaviors, and introduces our ADL model based methodology to check them. The automatic generation of test cases based on our straight-forward instruction representation is shown, and the efficient generation of them with good coverage is shown as well. The verification of the constraint checker, a very important tool for programmer, is performed. Results show that the toolkit can find some errors in previous delivery tools, and the introduced methodology verifies the feasibility of our instruction set specification.

Effect of Specific Verbal Instructions on the Identification of Pain Location during a Passive Straight Leg Raise Test

Musculoskeletal pain is common. Because pain is subjective, objectively describing it is crucial. However, pain assessment may cause distress in patients;therefore, physical therapists (PTs) should conduct these tests quickly and accurately. Simple and clear instructions are recommended for pain assessment. However, few studies have provided evidence to support this hypothesis. Correspondingly, this study aimed to confirm the effectiveness of specific verbal instructions for pain location during five consecutive Passive Straight Leg Raise (PSLR) tests. The 28 asymptomatic participants (age 27.4 ± 9.6 years) who provided informed consent received five consecutive PSLR tests: three without and two with specific verbal instructions to ascertain pain intensity, quality, and location. The participants drew pain locations on a body chart and described the pain intensity and quality after each test. All participants were interviewed regarding the differences they noted in the presence and absence of specific verbal instructions. Each pain location was classified into one of ten areas for statistical analysis. The proportion of participants who changed the pain location was compared between the tests using McNemar’s test, and the kappa coefficient was confirmed for consistency of pain location. There was a significant difference in the proportion of participants who changed their pain location between the second and third tests and from the third to the fourth test (McNemar’s test: p = 0.003). Kappa coefficients had low consistency (κ = 0.28) just after receiving the specific verbal instructions in the fourth test compared to the third test. Consistency improved in the fifth test (κ = 0.57);93% of the participants answered that the pain location had become clearer. This study revealed the effects of specific verbal instructions in identifying pain locations. This detailed information may help PTs provide appropriate treatment and contribute to reducing pain in clinical settings.

A TSE based design for MMSE and QRD of MIMO systems based on ASIP

A Taylor series expansion(TSE) based design for minimum mean-square error(MMSE) and QR decomposition(QRD) of multi-input and multi-output(MIMO) systems is proposed based on application specific instruction set processor(ASIP), which uses TSE algorithm instead of resource-consuming reciprocal and reciprocal square root(RSR) operations.The aim is to give a high performance implementation for MMSE and QRD in one programmable platform simultaneously.Furthermore, instruction set architecture(ISA) and the allocation of data paths in single instruction multiple data-very long instruction word(SIMD-VLIW) architecture are provided, offering more data parallelism and instruction parallelism for different dimension matrices and operation types.Meanwhile, multiple level numerical precision can be achieved with flexible table size and expansion order in TSE ISA.The ASIP has been implemented to a 28 nm CMOS process and frequency reaches 800 MHz.Experimental results show that the proposed design provides perfect numerical precision within the fixed bit-width of the ASIP, higher matrix processing rate better than the requirements of 5G system and more rate-area efficiency comparable with ASIC implementations.