The key parameters of vertical AlN Schottky barrier diodes(SBDs) with variable drift layer thickness(DLT) and drift layer concentration(DLC) are investigated. The specific on-resistance(R_(on,sp)) decreased to 0.5 mΩ...The key parameters of vertical AlN Schottky barrier diodes(SBDs) with variable drift layer thickness(DLT) and drift layer concentration(DLC) are investigated. The specific on-resistance(R_(on,sp)) decreased to 0.5 mΩ · cm^(2) and the breakdown voltage(V_(BR)) decreased from 3.4 kV to 1.1 kV by changing the DLC from 10^(15) cm^(-3) to 3×10^(16) cm^(-3). The VBRincreases from 1.5 kV to 3.4 kV and the Ron,sp also increases to 12.64 mΩ · cm^(2) by increasing DLT from 4-μm to 11-μm. The VBRenhancement results from the increase of depletion region extension. The Baliga's figure of merit(BFOM) of3.8 GW/cm^(2) was obtained in the structure of 11-μm DLT and 10^(16) cm^(-3) DLC without FP. When DLT or DLC is variable,the consideration of the value of BFOM is essential. In this paper, we also present the vertical AlN SBD with a field plate(FP), which decreases the crowding of electric field in electrode edge. All the key parameters were optimized by simulating based on Silvaco-ATLAS.展开更多
A variable-K trenches silicon-on-insulator(SOI)lateral diffused metal-oxide-semiconductor field-effect transistor(MOSFET)with a double conductive channel is proposed based on the enhancement of low dielectric constant...A variable-K trenches silicon-on-insulator(SOI)lateral diffused metal-oxide-semiconductor field-effect transistor(MOSFET)with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields.The device features variable-K dielectric double trenches and a P-pillar between the trenches(VK DT-P LDMOS).The low-K dielectric layer on the surface increases electric field of it.Adding a variable-K material introduces a new electric field peak to the drift region,so as to optimize electric field inside the device.Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it.Thereby,breakdown voltage(BV)of the device is increased.The double conductive channels provide two current paths that significantly reduce specific on-resistance(Ron,sp).Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ·cm^2.The Ron,sp of VK DT-P LDMOS is reduced by 78.9%compared with the conventional structure.展开更多
基金supported by Key-Area Research and Development Program of Guangdong Province,China (Grant Nos. 2020B010174001 and 2020B010171002)Ningbo Science and Technology Innovation 2025 (Grant No. 2019B10123)。
文摘The key parameters of vertical AlN Schottky barrier diodes(SBDs) with variable drift layer thickness(DLT) and drift layer concentration(DLC) are investigated. The specific on-resistance(R_(on,sp)) decreased to 0.5 mΩ · cm^(2) and the breakdown voltage(V_(BR)) decreased from 3.4 kV to 1.1 kV by changing the DLC from 10^(15) cm^(-3) to 3×10^(16) cm^(-3). The VBRincreases from 1.5 kV to 3.4 kV and the Ron,sp also increases to 12.64 mΩ · cm^(2) by increasing DLT from 4-μm to 11-μm. The VBRenhancement results from the increase of depletion region extension. The Baliga's figure of merit(BFOM) of3.8 GW/cm^(2) was obtained in the structure of 11-μm DLT and 10^(16) cm^(-3) DLC without FP. When DLT or DLC is variable,the consideration of the value of BFOM is essential. In this paper, we also present the vertical AlN SBD with a field plate(FP), which decreases the crowding of electric field in electrode edge. All the key parameters were optimized by simulating based on Silvaco-ATLAS.
基金Project supported by the Scientific Research Fund of Hunan Provincial Education Department,China(Grant No.19K001).
文摘A variable-K trenches silicon-on-insulator(SOI)lateral diffused metal-oxide-semiconductor field-effect transistor(MOSFET)with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields.The device features variable-K dielectric double trenches and a P-pillar between the trenches(VK DT-P LDMOS).The low-K dielectric layer on the surface increases electric field of it.Adding a variable-K material introduces a new electric field peak to the drift region,so as to optimize electric field inside the device.Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it.Thereby,breakdown voltage(BV)of the device is increased.The double conductive channels provide two current paths that significantly reduce specific on-resistance(Ron,sp).Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ·cm^2.The Ron,sp of VK DT-P LDMOS is reduced by 78.9%compared with the conventional structure.
