The TMT tertiary mirror system is facing a challenge of a rigid requirement for image jitter performance. The design of the mechanical structure and the devices selection will affect the image motion jitter for the te...The TMT tertiary mirror system is facing a challenge of a rigid requirement for image jitter performance. The design of the mechanical structure and the devices selection will affect the image motion jitter for the telescope observation. In this paper, a jitter test experiment has been done on a similar configuration telescope to support the design of the TMT tertiary mirror system. A method of position tracking is explored for jitter test using a 32bit absolute angle encoder. Several kinds of disturbance sources which can affect the system jitter have been discussed. According to the experimental results, during the low speed tracking, the jitter is less than 10 milliarcsec RMS, and the design of the system can meet the jitter requirement the TMT tertiary mirror system. The NFIRAOS error rejection transfer function is given for the further correction of jitter.展开更多
基金Sponsored by the National Natural Science Foundation of China( Grant No.11403022).
文摘The TMT tertiary mirror system is facing a challenge of a rigid requirement for image jitter performance. The design of the mechanical structure and the devices selection will affect the image motion jitter for the telescope observation. In this paper, a jitter test experiment has been done on a similar configuration telescope to support the design of the TMT tertiary mirror system. A method of position tracking is explored for jitter test using a 32bit absolute angle encoder. Several kinds of disturbance sources which can affect the system jitter have been discussed. According to the experimental results, during the low speed tracking, the jitter is less than 10 milliarcsec RMS, and the design of the system can meet the jitter requirement the TMT tertiary mirror system. The NFIRAOS error rejection transfer function is given for the further correction of jitter.
文摘提出了一种应用于高速串行链路中的基于二阶预加重和阻抗校正技术的6 Gbit/s低功耗低抖动电压模(VM)发送器。在综合分析阻抗、供电电流和输出驱动器预加重等因素影响的基础上,采用了多种技术来提高发送器的信号完整性,主要包括:设计了一种阻抗校正电路(ICU)以保证50Ω的输出阻抗并抑制信号反射,提出了一种自偏置稳压器用来稳定电源电压,同时设计了一种信号边沿驱动器用以加速信号的转换时间。最终,整个发送器在65 nm CMOS工艺平台进行设计。后仿真结果表明,发送器工作在6 Gbit/s时,远端输出眼图高度大于800 m V,均方根抖动小于2.70 ps。发送器的功耗为16.1 m A,占用面积仅为370μm×230μm。
