An integrated split and dummy gates MOSFET with fast turn-off and reverse recovery characteristics

A power MOSFET with integrated split gate and dummy gate(SD-MOS) is proposed and demonstrated by the TCAD SENTAURUS.The split gate is surrounded by the source and shielded by the dummy gate.Consequently,the coupling area between the split gate and the drain electrode is reduced,thus the gate-to-drain charge(Q_(GD)),reverse transfer capacitance(C_(RSS)) and turn-off loss(E_(off)) are significantly decreased.Moreover,the MOS-channel diode is controlled by the dummy gate with ultra-thin gate oxide t_(ox),which can be turned on before the parasitic P-base/N-drift diode at the reverse conduction,then the majority carriers are injected to the N-drift to attenuate the minority injection.Therefore,the reverse recovery charge(Q_(RR)),time(T_(RR)) and peak current(I_(RRM)) are effectively reduced at the reverse freewheeling state.Additionally,the specific on-resistance(R_(on,sp)) and breakdown voltage(BV) are also studied to evaluate the static properties of the proposed SD-MOS.The simulation results show that the Q_(GD) of 6 nC/cm^(2),the C_(RSS) of 1.1 pF/cm^(2) at the V_(DS) of 150 V,the QRR of 1.2 μC/cm^(2) and the R_(on,sp) of 8.4 mΩ·cm^(2) are obtained,thus the figures of merit(FOM) including Q_(GD) ×R_(on,sp) of50 nC·mΩ,E_(off) × R_(on,sp) of 0.59 mJ·mΩ and the Q_(RR) × R_(on,sp) of 10.1 μC·mΩ are achieved for the proposed SD-MOS.

A SiC asymmetric cell trench MOSFET with a split gate and integrated p^(+)-poly Si/SiC heterojunction freewheeling diode

A new SiC asymmetric cell trench metal–oxide–semiconductor field effect transistor(MOSFET)with a split gate(SG)and integrated p^(+)-poly Si/SiC heterojunction freewheeling diode(SGHJD-TMOS)is investigated in this article.The SG structure of the SGHJD-TMOS structure can effectively reduce the gate-drain capacitance and reduce the high gateoxide electric field.The integrated p^(+)-poly Si/SiC heterojunction freewheeling diode substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device.Numerical analysis results show that,compared with the conventional asymmetric cell trench MOSFET(CA-TMOS),the high-frequency figure of merit(HF-FOM,R_(on,sp)×Q_(gd,sp))is reduced by 92.5%,and the gate-oxide electric field is reduced by 75%.In addition,the forward conduction voltage drop(V_(F))and gate-drain charge(Q_(gd))are reduced from 2.90 V and 63.5μC/cm^(2) in the CA-TMOS to 1.80 V and 26.1μC/cm^(2) in the SGHJD-TMOS,respectively.Compared with the CA-TMOS,the turn-on loss(E_(on)) and turn-off loss(E_(off)) of the SGHJD-TMOS are reduced by 21.1%and 12.2%,respectively.

A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance

A split gate MOSFET(SG-MOSFET)is widely known for reducing the reverse transfer capacitance(C_(RSS)).In a 3.3 kV class,the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field.In addition to the poor static performance,the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering(DIBL)caused by the high gate oxide electric field.As such,a 3.3 kV 4 H-SiC split gate MOSFET with a grounded central implant region(SG-CIMOSFET)is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance.The SG-CIMOSFET has a significantly low on-resistance(R_(ON))and maximum gate oxide field(E_(OX))due to the central implant region.A grounded central implant region significantly reduces the C_(RSS)and gate drain charge(Q_(GD))by partially screening the gate-to-drain capacitive coupling.Compared to a planar MOSFET,the SG MOSFET,central implant MOSFET(CIMOSFET),the SGCIMOSFET improve the R_(ON)×Q_(GD)by 83.7%,72.4%and 44.5%,respectively.The results show that the device features not only the smallest switching energy loss but also the fastest switching time.

A novel enhancement mode AlGaN/GaN high electron mobility transistor with split floating gates

A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.

A novel power UMOSFET with a variable K dielectric layer

A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on=state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS device. Numerical simulation results indicate that the proposed device features high performance with an improved figure of merit of Qg × RON and BV^2/RON, as compared with the previous power UMOSFET.

Planar split dual gate MOSFET

A new planar split dual gate （PSDG） MOSFET device, its characteristics and experimental results, as well as the three dimensional device simulations, are reported here for the first time. Both theoretical calculation and 3D simulation, as well as the experiment data, show that the two independent split dual gates can provide dynamical control of the device characteristics, such as threshold voltage （Vt） and sub-threshold swing （SS）, as well as the device saturated current. The PSDG MOSFET transistor leakage current （loft） can be reduced as much as 78% of the traditional single gate MOSFET. The PSDG is fabricated and fully compatible with our conventional 0.18 μm logic process flow.

An LDMOS with large SOA and low specific on-resistance

An LDMOS with nearly rectangular-shape safe operation area （SOA） and low specific on-resistance is proposed. By utilizing a split gate, an electron accumulation layer is formed near the surface of the n-drift region to improve current conduction capability during on-state operation. As a result, the specific on-resistance can be low- ered down to 74.7 m^2.cm2 for a 600 V device from simulation. Furthermore, under high-voltage and high-current conditions, electrons and holes flow as majority carriers in the n-drift region and p-type split gate, respectively. Due to charge compensation occurring between holes and electrons, the local electric field is reduced and impact ion- ization is weakened in the proposed device. Therefore, a higher on-state breakdown voltage at large V6s is obtained and snap-back is suppressed as well.