In this paper,massive state-of-theart planar power dividers are presented and discussed. The innovations of these superiorly-performanced power dividers lie in the performance breakthrough,physical configurations and ...In this paper,massive state-of-theart planar power dividers are presented and discussed. The innovations of these superiorly-performanced power dividers lie in the performance breakthrough,physical configurations and function integrations. Eventually,based on the trend presented,the future of the power dividers is predicted. This paper might have inspiration significance to illuminate the way for the development of power dividers.展开更多
A layout and connection optimization for static frequency divider is presented. The layout optimization provides a new circle topology transistors placement and reasonable connection structure, which reduces the paras...A layout and connection optimization for static frequency divider is presented. The layout optimization provides a new circle topology transistors placement and reasonable connection structure, which reduces the parasitic effectively and enables self-oscillation frequency enhancement. Besides, bandwidth enhancement techniques based on a center-tap capacitor in input balun design and inductive peaking in latch design are adopted to improve further high frequency performance with low power consumption. As a proof of concept, design of a divide-by-2 static frequency divider in 0.13 μm SiGe BiCMOS technology is reported. With single-ended input clock signal, the divider is measured to be operated from 40 to 90 GHz. Phase noise measurements of a 90 GHz input clock signal indicate ideal behavior with no measurable noise contribution from the divider. The divider followed by a buffer that can deliver more than-10 dBm output power, which is sufficient to drive succeeding stage. To the author's knowledge, the divider exhibits a competitive power dissipation and the highest FOM among silicon based frequency dividers that operating higher than 70 GHz.展开更多
A fault-tolerant circuit is required for robust quantum computing in the presence of noise.Clifford+T circuits are widely used in fault-tolerant implementations.As a result,reducing T-depth,T-count,and circuit width h...A fault-tolerant circuit is required for robust quantum computing in the presence of noise.Clifford+T circuits are widely used in fault-tolerant implementations.As a result,reducing T-depth,T-count,and circuit width has emerged as important optimization goals.A measure-and-fixup approach yields the best T-count for arithmetic operations,but it requires quantum measurements.This paper proposes approximate Toffoli,TR,Peres,and Fredkin gates with optimized T-depth and T-count.Following that,we implement basic arithmetic operations such as quantum modular adder and subtractor using approximate gates that do not require quantum measurements.Then,taking into account the circuit width,T-depth,and T-count,we design and optimize the circuits of two multipliers and a divider.According to the comparative analysis,the proposed multiplier and divider circuits have lower circuit width,T-depth,and T-count than the current works that do not use the measure-and-fixup approach.Significantly,the proposed second multiplier produces approximately 77%T-depth,60%T-count,and 25%width reductions when compared to the existing multipliers without quantum measurements.展开更多
基金supported by National Basic Research Program of China(973 Program)(No.2014CB339900)National Natural Science Foundations of China(No.61422103,No.61671084,and No.61327806)
文摘In this paper,massive state-of-theart planar power dividers are presented and discussed. The innovations of these superiorly-performanced power dividers lie in the performance breakthrough,physical configurations and function integrations. Eventually,based on the trend presented,the future of the power dividers is predicted. This paper might have inspiration significance to illuminate the way for the development of power dividers.
基金supported by National Natural Science Foundation of China under Grant 61701114the National Science and Technology Major Project under Grant 2017ZX03001020the Scientific Research Foundation of Graduate School of Southeast University (Grant No. YBJJ1811)
文摘A layout and connection optimization for static frequency divider is presented. The layout optimization provides a new circle topology transistors placement and reasonable connection structure, which reduces the parasitic effectively and enables self-oscillation frequency enhancement. Besides, bandwidth enhancement techniques based on a center-tap capacitor in input balun design and inductive peaking in latch design are adopted to improve further high frequency performance with low power consumption. As a proof of concept, design of a divide-by-2 static frequency divider in 0.13 μm SiGe BiCMOS technology is reported. With single-ended input clock signal, the divider is measured to be operated from 40 to 90 GHz. Phase noise measurements of a 90 GHz input clock signal indicate ideal behavior with no measurable noise contribution from the divider. The divider followed by a buffer that can deliver more than-10 dBm output power, which is sufficient to drive succeeding stage. To the author's knowledge, the divider exhibits a competitive power dissipation and the highest FOM among silicon based frequency dividers that operating higher than 70 GHz.
基金This work was supported by the National Natural Science Foundation of China(Grant Nos.61762012,61763014,and 62062035)the Science and Technology Project of Guangxi(Grant No.2020GXNSFDA238023).
文摘A fault-tolerant circuit is required for robust quantum computing in the presence of noise.Clifford+T circuits are widely used in fault-tolerant implementations.As a result,reducing T-depth,T-count,and circuit width has emerged as important optimization goals.A measure-and-fixup approach yields the best T-count for arithmetic operations,but it requires quantum measurements.This paper proposes approximate Toffoli,TR,Peres,and Fredkin gates with optimized T-depth and T-count.Following that,we implement basic arithmetic operations such as quantum modular adder and subtractor using approximate gates that do not require quantum measurements.Then,taking into account the circuit width,T-depth,and T-count,we design and optimize the circuits of two multipliers and a divider.According to the comparative analysis,the proposed multiplier and divider circuits have lower circuit width,T-depth,and T-count than the current works that do not use the measure-and-fixup approach.Significantly,the proposed second multiplier produces approximately 77%T-depth,60%T-count,and 25%width reductions when compared to the existing multipliers without quantum measurements.
