This paper mainly introduces an output control method with high stable precision of a large power IGBT arc welding inverter. Experiments indicate that this kind of control mode can effectively improve the static and d...This paper mainly introduces an output control method with high stable precision of a large power IGBT arc welding inverter. Experiments indicate that this kind of control mode can effectively improve the static and dynamic characteristics and stability of power supply system. And it can decrease the spatters in the welding process apparently. This power supply is especially suitable to automatic robot welding assembly line. It will be the developing direction of robot welding supply in the future.展开更多
针对窄频差硅基环形波动陀螺动态性能差的问题,提出了一种基于比例积分微分-惯性环节(proportion integral differential-inertial element,PID-IE)的串联式相位校正检测闭环系统控制器。以硅微机械陀螺仪结构运动方程为基础建立了理想...针对窄频差硅基环形波动陀螺动态性能差的问题,提出了一种基于比例积分微分-惯性环节(proportion integral differential-inertial element,PID-IE)的串联式相位校正检测闭环系统控制器。以硅微机械陀螺仪结构运动方程为基础建立了理想的窄频差U形弹性梁硅基环形波动陀螺仪的系统模型。通过对环形陀螺开环工作状态下的系统模型及其外围电路的传递函数和波特图分析,设计了一种基于PID-IE的检测闭环系统控制器。通过对其系统模型及外围电路时域仿真,验证了该检测闭环控制系统的可行性,通过仿真发现,加入该控制器后的陀螺输出稳定时间减少了50%,陀螺检测位移输出减小了2个数量级,基本实现了该陀螺的检测位移抑制。在模拟电路中实现了该检测闭环控制系统后,通过实验测试了陀螺检测闭环控制前后的各项性能指标。通过实验测试发现,实现闭环控制后,陀螺输出稳定时间约为0.15 s,陀螺检测位移在闭环工作状态下比开环工作状态减小了97%,陀螺的标度因数比检测开环提高了10倍,零偏及零偏不稳定性与检测开环相比分别提升了3倍和8倍,且闭环控制系统的工作带宽比开环工作带宽提高了30倍。展开更多
This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structur...This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.展开更多
文摘This paper mainly introduces an output control method with high stable precision of a large power IGBT arc welding inverter. Experiments indicate that this kind of control mode can effectively improve the static and dynamic characteristics and stability of power supply system. And it can decrease the spatters in the welding process apparently. This power supply is especially suitable to automatic robot welding assembly line. It will be the developing direction of robot welding supply in the future.
文摘针对窄频差硅基环形波动陀螺动态性能差的问题,提出了一种基于比例积分微分-惯性环节(proportion integral differential-inertial element,PID-IE)的串联式相位校正检测闭环系统控制器。以硅微机械陀螺仪结构运动方程为基础建立了理想的窄频差U形弹性梁硅基环形波动陀螺仪的系统模型。通过对环形陀螺开环工作状态下的系统模型及其外围电路的传递函数和波特图分析,设计了一种基于PID-IE的检测闭环系统控制器。通过对其系统模型及外围电路时域仿真,验证了该检测闭环控制系统的可行性,通过仿真发现,加入该控制器后的陀螺输出稳定时间减少了50%,陀螺检测位移输出减小了2个数量级,基本实现了该陀螺的检测位移抑制。在模拟电路中实现了该检测闭环控制系统后,通过实验测试了陀螺检测闭环控制前后的各项性能指标。通过实验测试发现,实现闭环控制后,陀螺输出稳定时间约为0.15 s,陀螺检测位移在闭环工作状态下比开环工作状态减小了97%,陀螺的标度因数比检测开环提高了10倍,零偏及零偏不稳定性与检测开环相比分别提升了3倍和8倍,且闭环控制系统的工作带宽比开环工作带宽提高了30倍。
文摘This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
