Ground movement induced by triple stacked tunneling with different construction sequences

This study tried to explore the ground movement induced by triple stacked tunneling(TST) with different construction sequences. A case study in Tianjin, China was used to investigate the ground movement during the TST(upper tunneling(UT)). For this, a modified Peck formula was proposed to predict the surface settlement induced by TST. Next, three sets of finite element analyses(FEA) were used to compare the effects of construction sequences(i.e. UT, middle tunneling(MT), and lower tunneling(LT)) on vertical and lateral ground displacements. The results of Tianjin case and UT reveal that compared to a Gaussian distribution for a single tunnel, the surface settlement curve of triple stacked tunnels is a bimodal distribution. It seems that the proposed modified Peck formula can effectively predict the surface settlement induced by TST. The results of the three sets of FEA demonstrate that the construction sequence has a significant influence on the ground movement. Among the three construction sequences, the largest lateral displacement is observed in the MT and the smallest one in UT.The existing tunnel has an inhibitory effect on the vertical displacement. The maximum value of the lateral displacement occurs at the depth of the new tunnel in each construction sequence.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO_2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.

Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.