A static frequency divider is presented using 0.7μm lnP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 ×0.65 mm^2. T...A static frequency divider is presented using 0.7μm lnP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 ×0.65 mm^2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.展开更多
Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology’s ability to implement high speed digital and integrated high performa...Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology’s ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2：1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic（CML） with 30 transistors.The circuit operated at a peak clock frequency of 40 GHz and dissipated 650 mW from a single -5 V supply.展开更多
文摘A static frequency divider is presented using 0.7μm lnP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 ×0.65 mm^2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.
文摘Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology’s ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2：1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic（CML） with 30 transistors.The circuit operated at a peak clock frequency of 40 GHz and dissipated 650 mW from a single -5 V supply.
