Space Charges Effect of Static Induction Transistor

The space charge effect (SCE) of static induction transistor (SIT) that occurs in high current region is systematically studied.The I V equations are deduced and well agree with experimental results.Two kinds of barriers are presented in SIT,corresponding to channel voltage barrier control (CVBC) mechanism and space charge limited control (SCLC) mechanism respectively.With the increase of drain voltage,the gradual transferring of operational mechanism from CVBC to SCLC is demonstrated.It points out that CVBC mechanism and its contest relationship with space charge barrier makes the SIT distinctly differentiated from JFET and triode devices,etc.The contest relationship of the two potential barriers also results in three different working regions,which are distinctly marked and analyzed.Furthermore,the extreme importance of grid voltage on SCE is illustrated.

Static Induction Devices with Planar Type Buried Gate

Based on the surface-gate and buried-gate structures,a novel buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed.An approach to realize a buried-gate type static induction transistor by conventional planar process technology is presented.Using this structure,it is successfully avoided the second epitaxy with a high degree of difficulty and the complicated mesa process in conventional buried gate.The experimental results demonstrate that this structure is desirable for application in power SIDs.Its advantages are high breakdown voltage and blocking gain.

Electrical Performance of Static Induction Transistor with Mixed I-V Characteristics

The mixed non-saturating I-V characteristics of static induction transistor (SIT) are investigated.The optimum matching relations among the structural,material,and technological parameters are also presented.The technological experiments demonstrate that the channel parameters play a critical role in determining whether it is a mixed,triode-like or pentode-like I-V characteristics.The general control principles,methods,and criterions of fabrication parameters as well as the effect of control factor are analytically discussed.The results are useful for design and fabrication of SIT,especially for SIT with mixed I-V characteristics.

Improvements on High Current Performance of Static Induction Transistor

Methods for improving the high current performance of static induction transistor （SIT） are presented.Many important factors,such as ＂trans-conductance per unit channel width＂ θ, ＂gate efficiency＂ η, ＂sensitivity factor＂ D,and ＂intrinsic static gain＂ μ0,that may be used to describe different aspects of the electrical performance of an SIT are first defined.The dependences of electrical parameters on the structure and technological process of an SIT are revealed for the first time.The packaging technologies are so important for the improvement of high power performance of SITs that they must be paid attention.Testing techniques and circuits for measuring frequency and power parameters of SITs are designed and constructed.The influence of packaging processes in technological practice on the electrical performance of SITs is also discussed in depth.

A Microwave High Power Static Induction Transistor with Double Dielectrics Gate Structure

The designing approaches and key fabricating technologies for high frequency high power double dielectrics gate static induction transistor (DDG SIT) with mixed non-saturating I-V characteristics are presented.The effects of parasitic gate-source capacitance (C gs) on the power performance of SIT are discussed.The main methods and considerations to diminish C gs,consequently to improve the high power performance are given.Synchronous epitaxy technology is the critical step to decrease C gs.The 7-μm pitch DDG SIT delivering output power >20W with >7dB power gain and >70% drain efficiency at 400MHz,and delivering output power >7W with >5dB power gain and >50% drain efficiency at 700MHz are successfully fabricated.

Analysis on Characteristic of Static Induction Transistor Using Mirror Method

A cylindrical gates model of the static induction transistor is proposed and mirror method is used to calculate the distribution of electric potential.The results show that:the potential barrier is directly determined by channel over pinched-off factor;gate efficiency η decreases as the gate dimension α 2 and shifted gate voltage are minished,and what differs from the first-order theory is that η will tend to zero at the shifted gate voltage tends to zero when V D=0;at low current,the voltage amplification factor μ increases as the drain current rising.When the drain current reaches certain degree,the voltage amplification factor keeps almost constant.In the end,an analytical description of SIT’s characteristic suited to both triode-like and mixed I-V characteristics are obtained.The predicted I-V curves are consistent perfectly with the reported experimental ones.

Experimental analysis of operating characteristics of organic semiconductor static induction transistor

The organic static induction transistor （OSIT） fabricated with organic semiconductor material copper-phthalocyanine （CuPc） is discussed in the paper. It has Schottky Gate electrode and sandwich structure of Au/CuPc/Al/CuPc/Au/glass. The operation mechanism of the device is studied on the physical model with practical parameters. Potential distribution and field intensity distribution in the conduction channel are computed by using finite-element method. By processing static experimental data with some mathematic tools, the V-I expression of CuPc/Al Schottky Gate is obtained and it is verified that OSIT has insaturation current property along with the increase of Drain bias voltage. By using AC small signal circuit model and appropriate numerical simulation method, the dynamic operating characteristics are investigated, and some influenced factors are analyzed.

Thermal analytic model of current gain for bipolar junction transistor-bipolar static induction transistor compound device

This paper proposes a thermal analytical model of current gain for bipolar junction transistor-bipolar static induction transistor （BJT-BSIT） compound device in the low current operation. It also proposes a best thermal compensating factor to the compound device that indicates the relationship between the thermal variation rate of current gain and device structure. This is important for the design of compound device to be optimized. Finally, the analytical model is found to be in good agreement with numerical simulation and experimental results. The test results demonstrate that thermal variation rate of current gain is below 10% in 25 ℃-85 ℃ and 20% in -55 ℃-25 ℃.

Dependence of transient performance on potential distribution in a static induction thyristor channel

The impact of potential barrier distribution on the transient performance of a static induction thyristor （SITH） in a channel determined by geometrical parameters and applied bias voltage is studied theoretically and experimentally. The analytical expressions of potential barrier height and the I-V characteristics of the SITH are also derived. The main factors that influence the transient performance of the SITH between the blocking and conducting states, as well as the mechanism underlying the transient process, is thoroughly investigated. This is useful in designing, fabricating, optimizing and applying SITHs properly.

Physical effect of carrier distribution in the channel of static induction thyristor

The physical effects of the carrier distribution in the channel on the dynamical performance of a static induction thyristor （SITH） have been studied numerically and experimentally. The analytical expressions of the minority carrier distribution in the channel of the SITH were also derived and the space charge distribution control- ling mechanism on the current of the SITH under high level injection have been analyzed deeply. The relationships among the minority carrier distribution, potential distribution, I-V characteristics and transient performances of the SITH are revealed.

A new static induction thyristor with high forward blocking voltage and excellent switching performances

A new static induction thyristor （SITH） with a strip anode region and p- buffer layer structure （SAP-B） has been successfully designed and fabricated. This structure is composed of a p- buffer layer and lightly doped n- regions embedded in the p＋-emitter. Compared with the conventional structure of a buffed-gate with a diffused source region （DSR buffed-gate）, besides the simple fabrication process, the forward blocking voltage of this SITH has been increased to 1600 V from the previous value of 1000 V, the blocking gain increased from 40 to 70, and the turn-offtime decreased from 0.8 to 0.4μs.

Improvement on the dynamical performance of a power bipolar static induction transistor with a buried gate structure

The failure of a bipolar static induction transistor （BSIT） often occurs in the transient process between the conducting-state and the blocking-state, so a profound understanding of the physical mechanism of the switching process is of significance for designing and fabricating perfect devices. The dynamical characteristics of the transient process between conducting-state and blocking-state BSITs are represented in detail in this paper. The influences of material, structural and technological parameters on the dynamical performances of BSITs are discussed. The mechanism underlying the transient conversion process is analyzed in depth. The technological approaches are developed to improve the dynamical characteristics of BSITs.

Improvements on high voltage performance of power static induction transistors

A novel structure for designing and fabricating a power static induction transistor（SIT）with excellent high breakdown voltage performance is presented.The active region of the device is designed to be surrounded by a deep trench to cut off the various probable parasitical effects that may degrade the device performance,and to avoid the parallel-current effect in particular.Three ring-shape junctions（RSJ）are arranged around the gate junction to reduce the electric field intensity.It is important to achieve maximum gate–source breakdown voltage BVGS, gate–drain breakdown voltage BVGD and blocking voltage for high power application.A number of technological methods to increase BVGD and BVGS are presented.The BVGS of the power SIT has been increased to 110 V from a previous value of 50–60 V,and the performance of the power SIT has been greatly improved.The optimal distance between two adjacent ring-shape junctions and the trench depth for the maximum BVGS of the structure are also presented.

Mechanism of Reverse Snapback on I-V Characteristics of Power SITHs with Buried Gate Structure

The reverse snapback phenomena （RSP） on I-V characteristics of static induction thyristors （SITH） are physically researched. The I-V curves of the power SITH exhibit reverse snapback phenomena, and even turn to the conducting-state,when the anode voltage in the forward blocking-state is increased to a critical value. The RSP I-V characteristics of the power SITH are analyzed in terms of operating mechanism, double carrier injection effect, space charge effect, electron-hole plasma in the channel, and the variation in carrier lifetime. The reverse snapback mechanism is theoretically pro- posed and the mathematical expressions to calculate the voltage and current values at the snapback point are presented. The computing results are compared with the experiment values.

An SIT-BJT Operation Model for SITh in the Blocking State

A SIT-BJT model is proposed for static induction thyristors （SITh） operation in the blocking state. On the basis of the physical mechanism, this model is presented analytically in terms of governing equations that link the electrical parameters to the structural parameters. The model is verified by numerical simulation and theoretical analysis. Based on the model, the variations of the electrical parameters such as the potential barrier, the anode junction voltage drop, and the current amplification factor are studied and discussed.

Photo-sensitive characteristics of negative resistance turn-around occurring in SIPTH

Influences of light irradiation on the negative resistance turn-around characteristics of static induction photosensitive thyristor （SIPTH） have been experimentally and theoretically studied. As the gate current of SIPTH is increased by the light irradiation, the potential barrier in the channel is reduced due to the increase in voltage drop across the gate series resistance. Therefore, SIPTH can be quickly switched from the blocking state to the conducting state by relatively low anode voltage. The optimal matching relation for controlling anode conducting voltage of SIPTH by light irradiation has also been represented.