Direct measurement and analysis of total ionizing dose effect on 130 nm PD SOI SRAM cell static noise margin

In this work, the total ionizing dose（TID） effect on 130 nm partially depleted（PD） silicon-on-insulator（SOI） static random access memory（SRAM） cell stability is measured. The SRAM cell test structure allowing direct measurement of the static noise margin（SNM） is specifically designed and irradiated by gamma-ray. Both data sides＇ SNM of 130 nm PD SOI SRAM cell are decreased by TID, which is different from the conclusion obtained in old generation devices that one data side＇s SNM is decreased and the other data side＇s SNM is increased. Moreover, measurement of SNM under different supply voltages（Vdd） reveals that SNM is more sensitive to TID under lower Vdd. The impact of TID on SNM under data retention Vddshould be tested, because Vddof SRAM cell under data retention mode is lower than normal Vdd.The mechanism under the above results is analyzed by measurement of I–V characteristics of SRAM cell transistors.

超深亚微米无负载四管与六管SRAMSNM的对比研究

采用基于物理的α指数MOSFET模型与低功耗传输域MOSFET模型,推导了新的超深亚微米无负载四管与六管SRAM存储单元静态噪声容限的解析模型,对比分析了由沟道掺杂原子本征涨落引起的相邻MOSFET的阈值电压失配对无负载四管和六管SRAM单元静态噪声容限的影响。

Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration

An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is chosen in order to make the access transistor operate in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The WNM shift amount is determined from the measured WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. Together with the maximum likelihood method, a normal distribution of the AWNM drastically improves development efficiency because the write failure probability can be estimated from a small number of samples. The effectiveness of the proposed method is verified using the Monte Carlo simulation.

An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling

We propose an accurate model to describe the I-V characteristics of a sub-90-nm metal-oxide-semiconductor field-effect transistor(MOSFET) in the linear and saturation regions for fast analytical calculation of the current.The model is based on the BSIM3v3 model.Instead of using constant threshold voltage and early voltage,as is assumed in the BSIM3v3 model,we define these voltages as functions of the gate-source voltage.The accuracy of the model is verified by comparison with HSPICE for the 90-,65-,45-,and 32-nm CMOS technologies.The model shows better accuracy than the nth-power and BSIM3v3 models.Then,we use the proposed I-V model to calculate the read static noise margin(SNM) of nano-scale conventional 6T static random-access memory(SRAM) cells with high accuracy.We calculate the read SNM by approximating the inverter transfer voltage characteristic of the cell in the regions where vertices of the maximum square of the butterfly curves are placed.The results for the SNM are also in excellent agreement with those of the HSPICE simulation for 90-,65-,45-,and 32-nm technologies.Verification in the presence of process variations and negative bias temperature instability(NBTI) shows that the model can accurately predict the minimum supply voltage required for a target yield.

一种用于FPGA配置的抗干扰维持电路

设计并实现了一种用于FPGA配置的抗干扰维持电路,针对基于SRAM的FPGA配置单元易受噪声影响丢失信息的问题,提出了电压不稳定、低压状态下配置信息的抗干扰维持方案.在设计高面积效率配置单元、分析噪声容限的基础上,得出配置单元静态噪声容限随电源电压单调递增的关系,并进一步设计了基准、电荷泵以及电压比较控制电路构成的可切换电源反馈控制电路,实现了配置单元的稳定供电.仿真及测试结果表明,正常工作电压为2.5V的FPGA芯片能在1.8V低电压下维持配置信息,提高了FPGA芯片的抗干扰性能.

新型高可靠性低功耗6管SRAM单元设计

提出一种新型的6管SRAM单元结构,该结构采用读/写分开技术,从而很大程度上解决了噪声容限的问题,并且该结构在数据保持状态下,采用漏电流以及正反馈保持数据,从而不需要数据的刷新来维持数据。仿真显示了正确的读/写功能,并且读/写速度和普通6管基本相同,但是比普通6管SRAM单元的读/写功耗下降了39%。

纳米工艺SRAM单元的尺寸效应研究与优化

集成电路工艺尺寸减小至纳米级时,尺寸效应的出现会导致SRAM读写可靠性下降。针对传统六管SRAM单元,采用蝶形曲线法对尺寸效应进行了分析,对不同工艺尺寸(90 nm^7 nm)的静态噪声容限进行了研究。分析了漏极致势垒降低效应、反向短沟道效应、正/负偏压温度不稳定性效应等物理效应,据此拟合出一个静态噪声容限经验公式。最后,对SRAM单元尺寸效应进行了优化,提高了SRAM单元的稳定性。

基于九管存储单元的嵌入式SRAM设计

为了解决深亚微米及纳米尺寸下SRAM设计在可靠性及其他性能方面所面临的挑战,在分析不同存储单元的基础上,提出了一种优化的具有高稳定性的九管存储单元,并采用9管存储阵列,设计了一款高可靠性的512×32位SRAM。基于TSMC 0.18μm CMOS工艺,对电路进行仿真。实验结果表明:该SRAM在250MHz工作频率下,存储阵列中数据的读写稳定性高,阵列功耗为7.76mW,数据读出时间为0.86ns,电路面积仅比采用传统6管单元增加13.5%。

近阈值标准单元库和其在传感网芯片中的应用

将电源电压降低到晶体管阈值电压附近可以有效提高数字电路的能效,而近阈值标准单元库是近阈值数字电路设计的基础。通过分析逻辑门间静态噪声容限的兼容性、逻辑门在宽电压范围下延时变化情况,并通过求解最大包问题等的相关算法,对现有的商用数字CMOS标准单元库进行有效筛选,得到适用于低电压工作的近阈值数字CMOS标准单元库。通过一个应用于传感网中的双电压域、双核微控制器流片测试,对此标准单元库进行了验证,结果显示其中工作在0.5 V下的高能效核的能量效率相较传统工作电压下提高到2.76倍。

超动态电压调整SRAM设计

本文设计了一种8管SRAM单元和相应的读写辅助电路,解决了传统6管SRAM单元低压工作存在的读写稳定性问题,实现了具有超动态电压调整(U-DVS)能力的SRAM的设计,其工作电压范围可从亚阈值区变化到标称电压,达到SRAM低功耗和高性能的平衡。通过自适应衬底偏置电路和读缓冲器的设计,增强了SRAM单元低压下的读稳定性和鲁棒性。设计了可复用的读写辅助电路,同时提高SRAM的低压写能力和读速度。采用标准0.18-μm CMOS工艺进行了流片验证。测试结果表明SRAM工作电压范围达到0.2V-1.8V,相应的工作频率为184 kHz-208 MHz,从1.8V到0.2V的工作电压范围内,SRAM总功耗降低了4个数量级,工作电压0.2V时的读写功耗仅为30nW。

Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications

The use of Internet of Things(IoT)applications become dominant in many systems.Its on-chip data processing and computations are also increasing consistently.The battery enabled and low leakage memory system at subthreshold regime is a critical requirement for these IoT applications.The cache memory designed on Static Random-Access Memory(SRAM)cell with features such as low power,high speed,and process tolerance are highly important for the IoT memory system.Therefore,a process tolerant SRAM cell with low power,improved delay and better stability is presented in this research paper.The proposed cell comprises 11 transistors designed with symmetric approach for write operations and single ended circuit for read operations that exhibits an average dynamic power saving of 43.55%and 47.75%for write and 35.59%and 36.56%for read operations compared to 6 T and 8 T SRAM cells.The cell shows an improved write delay of 26.46%and 37.16%over 6 T and 8T and read delay is lowered by 50.64%and 72.90%against 6 T and 10 T cells.The symmetric design used in core latch to improve the write noise margin(WNM)by 17.78%and 6.67%whereas the single ended separate read circuit improves the Read Static Noise Margin(RSNM)by 1.88x and 0.33x compared to 6 T and 8T cells.The read power delay product and write power delay product are lower by 1.94x,1.39x and 0.17x,2.02x than 6 T and 8 T cells respectively.The lower variability from 5000 samples validates the robustness of the proposed cell.The simulations are carried out in Cadence virtuoso simulator tool with Generic Process Design Kit(GPDK)45 nm technology file in this work.

Effect of Temperature &Supply Voltage Variation on Stability of 9T SRAM Cell at 45 nm Technology for Various Process Corners

Due to the continuous rising demand of handheld devices like iPods, mobile, tablets;specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) should have low power consumption and stability. As we are continuously moving towards scaling for the last two decades the effect of this is process variations which have severe effect on stability, performance. Reducing the supply voltage to sub-threshold region, which helps in reducing the power consumption to an extent but side by side it raises the issue of the stability of the memory. Static Noise Margin of SRAM cell enforces great challenges to the sub threshold SRAM design. In this paper we have analyzed the cell stability of 9T SRAM Cell at various processes. The cell stability is checked at deep submicron (DSM) technology. In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current. The effect has been observed at various process corners at 45 nm technology. The temperature has a significant effect on stability along with the Vdd. The Cell has been working efficiently at all process corners and has 50% more SNM from conventional 6T SRAM and 30% more WM from conventional 6T SRAM cell.

Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications

Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been introduced, 8T SRAM is one of them but it has its limitation like read disturbance. In this paper we have analyzed a novel PP based 9T SRAM at 45 nm technology. Cell which has 33% increased SVNM (Static Voltage Noise Margin) from 6T and also 22%.reduced leakage power. N curve analysis has been done to find the various stability factors. As compared to the 10T SRAM cell it is more area efficient.

FPGA配置SRAM设计技术

首先分析了配置SRAM在SRAM型FPGA中的作用,介绍了配置SRAM的单元结构及在设计中的要点。设计实现了一种基于65 nm工艺的SRAM结构,并针对读写能力、功耗、噪声给出相应的仿真结果。此电路结构具有低功耗、抗噪声能力强的优点,已被应用于FPGA设计中并流片成功。

An isolated SNM model for high-stability multi-port register file in 65 nm CMOS

In modern microprocessors, the multi-port register file is one of the key modules which provides fast and multiple data access for instructions. As the number of access ports in register files increases, stability becomes a key issue due to the voltage fluctuation on bit lines. We propose to apply an isolated inverter to address the voltage fluctuation. To assess the register stability, we derive a closed-form expression of static noise margin （SNM） for our register file. The proposed SNM model can be used as a guideline to predict the impact of several register parameters on the stability and optimize register file designs. To validate the proposed SNM model, we fabricated a test chip of two-write-four-read （2W4R） 1024 bits register file in a TSMC 65 nm low-power CMOS technology. The experimental result shows that the stability of our register file cells with an isolated inverter improve the conventional cells by approximately 2.4 times. Also, the supply voltage causes a fluctuation of SNM of about 65%, while temperature and transistor mismatch cause a fluctuation of SNM of about 20%.

A novel high reliability CMOS SRAM cell

A novel 8T single-event-upset（SEU） hardened and high static noise margin（SNM） SRAM cell is proposed. By adding one transistor paralleled with each access transistor,the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell.So the hold,read SNM and critical charge increase greatly.The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors.The hold and read SNM of the new cell increase by 72%and 141.7%,respectively,compared to the 6T design,but it has a 54%area overhead and read performance penalty.According to these features,this novel cell suits high reliability applications,such as aerospace and military.

A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process

A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage（200 mV） applications.Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes.To minimize leakage,a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty.Combined with buffering circuit and reconfigurable operation,the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region.Compared to the referenced subthreshold SRAM bitcell,the proposed bitcell shows：（1） a better critical state noise margin,and（2） smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13μW power consumption at 138 kHz frequency.