Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular be...Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.展开更多
In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temp...In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET's (L=4.2μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.展开更多
The effect of substrate doping on the threshold voltages of buried channel pMOSFET based on strained-SiGe technology was studied.By physically deriving the models of the threshold voltages,it is found that the layer w...The effect of substrate doping on the threshold voltages of buried channel pMOSFET based on strained-SiGe technology was studied.By physically deriving the models of the threshold voltages,it is found that the layer which inversely occurs first is substrate doping dependent,giving explanation for the variation of plateau observed in the C-V characteristics of this device,as the doping concentration increases.The threshold voltages obtained from the proposed model are-1.2805 V for buried channel and-2.9358 V for surface channel at a lightly doping case,and-3.41 V for surface channel at a heavily doping case,which agrees well with the experimental results.Also,the variations of the threshold voltages with several device parameters are discussed,which provides valuable reference to the designers of strained-SiGe devices.展开更多
文摘Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.
文摘In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET's (L=4.2μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.
基金Projects(51308040203,6139801)supported by the National Ministries and CommissionsProjects(72105499,72104089)supported the Fundamental Research Funds for the Central Universities,ChinaProject(2010JQ8008)supported by the Natural Science Basic Research Plan in Shaanxi Province,China
文摘The effect of substrate doping on the threshold voltages of buried channel pMOSFET based on strained-SiGe technology was studied.By physically deriving the models of the threshold voltages,it is found that the layer which inversely occurs first is substrate doping dependent,giving explanation for the variation of plateau observed in the C-V characteristics of this device,as the doping concentration increases.The threshold voltages obtained from the proposed model are-1.2805 V for buried channel and-2.9358 V for surface channel at a lightly doping case,and-3.41 V for surface channel at a heavily doping case,which agrees well with the experimental results.Also,the variations of the threshold voltages with several device parameters are discussed,which provides valuable reference to the designers of strained-SiGe devices.
