The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation res...The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.展开更多
A study of the gate current variation is presented for various thickness ultrathin gate oxides ranging from 1.9 to 3.0nm under the constant voltage stress.The experimental results show the stress induced leakage curre...A study of the gate current variation is presented for various thickness ultrathin gate oxides ranging from 1.9 to 3.0nm under the constant voltage stress.The experimental results show the stress induced leakage current(SILC) includes two parts.One is due to the interface trap-assisted tunneling.The other is owing to the oxide trap-assisted tunneling.展开更多
This paper studies the degradation of device parameters and that of stress induced leakage current （SILC） of thin tunnel gate oxide under channel hot electron （CHE） stress at high temperature by using n-channel me...This paper studies the degradation of device parameters and that of stress induced leakage current （SILC） of thin tunnel gate oxide under channel hot electron （CHE） stress at high temperature by using n-channel metal oxide semiconductor field effect transistors （NMOSFETs） with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and Vh degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.展开更多
文摘The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.
文摘A study of the gate current variation is presented for various thickness ultrathin gate oxides ranging from 1.9 to 3.0nm under the constant voltage stress.The experimental results show the stress induced leakage current(SILC) includes two parts.One is due to the interface trap-assisted tunneling.The other is owing to the oxide trap-assisted tunneling.
基金Project supported by the National Natural Science Foundation of China (Grant Nos 60736033 and 60506020)
文摘This paper studies the degradation of device parameters and that of stress induced leakage current （SILC） of thin tunnel gate oxide under channel hot electron （CHE） stress at high temperature by using n-channel metal oxide semiconductor field effect transistors （NMOSFETs） with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and Vh degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.
