A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults

A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits. Keywords delay fault - false path - redundancy - stuck-at fault Regular PaperThis work was funded in part by Motorola India Electronics Ltd., Bangalore 560042, India.An earlier version of this paper appeared in the Proceedings of the 12th Int. Coaf. VLSI Design, Jan. 1999.Subhashis Majumder is a professor and course leader for the Computer Science and Engineering Department of International Institute of Information Technology, Kolkata. He started his career in Texas Instruments India Pvt. Ltd. and has over seven years of industry experience. He received his M. Tech degree in computer science from the Indian Statistical Institute, Kolkata in 1996. His undergraduate work was done in the Electronics and Telecommunication Engineering Dept. of the Jadvpur University, Koikata. He also worked as a research assistant in the Computer Eng. Dept. of Rutgers University for a year. He has led product development teams working on protocol stack development as well as VoIP. His current areas of interest include delay fault testing, wire routing, partitioning, approximation algorithms, and application of computational geometry to CAD problems.Bhargab B. Bhattacharya received the B.Sc. degree in physics from the Presidency College, Calcutta, the B.Tech. and M.Tech. degrees in radiophysics and electronics, and the Ph.D. degree in computer science all from the University of Calcutta, India. Since 1982, he has been on the faculty of the Indian Statistical Institute, Calcutta, where currently he is a full professor. He visited the Department of Computer Science and Engineering, University of Nebraska-Lincoln, USA, during 1985–1987, and 2001–2002, and the Fault-Tolerant Computing Group, Institute of Informatics, at the University of Potsdam, Germany during 1998–2000. His research interest includes logic synthesis and testing of VLSI circuits, physical design, graph algorithms, and image processing architecture. He has published more than 130 papers in archival journals and refereed conference proceedings, and holds 6 United States patents. Currently, he is collaborating with Intel Corporation, USA, and IRISA, France, for development of image processing hardware and reconfigurable parallel computing tools. Dr. Bhattacharya is a fellow of the Indian National Academy of Engineering. He served on the conference committees of the International Test Conference (ITC), the Asian Test Symposium (ATS), the VLSI Design and Test Workshop (VDAT), the International Conference on Advanced Computing (ADCOMP), and the International Conference on High-Performance Computing (HiPC). For the International Conference on VLSI Design, he served as Tutorial Co-Chair (1994), Program Co-Chair (1997), General Co-Chair (2000), and as a member of the Steering Committee during 2001–2003. He is on the editorial board of the Journal of Circuits, Systems, and Computers (World Scientific, Singapore), and the Journal of Electronic Testing: Theory and Applications (Kluwer Academic Publishers, USA). [http://www.isical.ac.in/~bhargab]Vishwani D. Agrawal is the James J. Danaher Professor of Electrical and Computer Engineering at Auburn University, Alabama. He has over thirty years of industry and University experience, working at Bell Labs, Murray Hill, NJ; Rutgers University, New Brunswick, NJ; TRW, Redondo Beach, CA; IIT, Delhi, India; EG&G, Albuquerque. NM; and ATI, Champaign, IL. His areas of work include VLSI testing, lowpower design, and microwave antennas. He obtained his B.E. degree from the University of Roorkee (renamed as Indian Institute of Technology, Roorkee), India, in 1964; M.E. degree from the Indian Institute of Science, Bangalore, India, in 1966; and Ph.D. degree in electrical engineering from the University of Illinois, Urbana-Champaign, in 1971. He has published over 250 papers, has coauthored five books and holds thirteen United States patents. His textbook, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Kluwer Academic Publishers), co-authored with M. L. Bushnell, was published in 2000. He is the founder and Editor-in-Chief (1990-) of the Journal of Electronic Testing: Theory and Applications, and a past Editor-in-Chief (1985–87) of the IEEE Design & Test of Computers magazine. He is the Founder and Consulting Editor of the Frontiers in Electronic Testing Book Series of Kluwer Academic Publishers, Boston. He is a co-founder of the International Conference on VLSI Design, and the International Workshops on VLSI Design and Test, held annually in India. He has served on numerous conference committees and is a frequently invited speaker. He was the invited Plenary Speaker at the 1998 International Test Conference, Washington D.C., and the Keynote Speaker at the Ninth Asian Test Symposium in December 2000. During 1989 and 1990, he served on the Board of Governors of the IEEE Computer Society, and in 1994, chaired the Fellow Selection Committee of that Society. He has received seven Best Paper Awards and one Honorable Mention Paper Award. In 1998, he received the Harry H. Goode Memorial Award of the IEEE Computer Society, for innovative contributions to the field of electronic testing, and in 1993, received the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign, in recognition of his outstanding contributions in design and test of VLSI systems. Dr. Agrawal is a fellow of the IEEE, the ACM, and IETE-India. He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York. [http://www.ece.wisc.edu/~va]Michael L. Bushnell is a professor and a Board of Trustees Research Fellow in the Electrical and Computer Engineering Department at Rutgers University, New Jersey. He was also a Henry Rutgers Research Fellow. He has 24 years of industry and university experience, working at General Electric, Honeywell, Instron, Applicon, and Rutgers University. He received his Ph.D. degree in 1986 and his M.S. degree in 1983, both from Carnegie Mellon University. His undergraduate work was done at the Massachusetts Institute of Technology. He is a Presidential Young Investigator (1990) of the National Science Foundation of the United States. He is a co-author of 4 books (including the leading VLSI testing textbook entitled Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Kluwer Academic Publishers, 2000), co-authored with Vishwani Agrawal), 91 papers, and 7 patents. He is the co-author of two Prize Papers and one Honorable Mention paper. He served twice as Program Co-Chair of the International Conference on VLSI Design (1995 and 1996), and twice as the Conference Vice-Chair of the North Atlantic Test Workshop (2002 and 2003). His current VLSI CAD research interests are automatic mixed-signal circuit test-pattern generation, built-in self-testing, synthesis for testability, fault modeling for nano-technology, and low-power design. [http://www.ece.rutgers.edu/directory/bushnell.html]

Cellular automata basedmulti-bit stuck-at fault diagnosis for resistive memory

This paper presents a group-based dynamic stuck-at fault diagnosis scheme intended for resistive randomaccess memory(ReRAM).Traditional static random-access memory,dynamic random-access memory,NAND,and NOR flash memory are limited by their scalability,power,package density,and so forth.Next-generation memory types like ReRAMs are considered to have various advantages such as high package density,non-volatility,scalability,and low power consumption,but cell reliability has been a problem.Unreliable memory operation is caused by permanent stuck-at faults due to extensive use of write-or memory-intensive workloads.An increased number of stuck-at faults also prematurely limit chip lifetime.Therefore,a cellular automaton(CA)based dynamic stuck-at fault-tolerant design is proposed here to combat unreliable cell functioning and variable cell lifetime issues.A scalable,block-level fault diagnosis and recovery scheme is introduced to ensure readable data despite multi-bit stuck-at faults.The scheme is a novel approach because its goal is to remove all the restrictions on the number and nature of stuck-at faults in general fault conditions.The proposed scheme is based on Wolfram’s null boundary and periodic boundary CA theory.Various special classes of CAs are introduced for 100%fault tolerance:single-lengthcycle single-attractor cellular automata(SACAs),single-length-cycle two-attractor cellular automata(TACAs),and single-length-cycle multiple-attractor cellular automata(MACAs).The target micro-architectural unit is designed with optimal space overhead.

Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study

This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set;this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.