Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The ...Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.);these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part;similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite;compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 2<sup>2</sup> = 4 combination of controlling is done (i.e.);both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits.展开更多
针对时钟偏差问题,提出基于双向到达时间(Two-way time of arrival,TW-ToA)测量的目标定位算法(Target Localization-based on TW-ToA,TL-TW-ToA)。TL-TW-TOA算法考虑了周转时间和时钟偏差问题。由于利用直接处理方法难以获取目标位置...针对时钟偏差问题,提出基于双向到达时间(Two-way time of arrival,TW-ToA)测量的目标定位算法(Target Localization-based on TW-ToA,TL-TW-ToA)。TL-TW-TOA算法考虑了周转时间和时钟偏差问题。由于利用直接处理方法难以获取目标位置的最优解,TL-TW-TOA算法选用次优、强健算法进行近似,并将定位问题建立成广义信赖域次优问题(Generalized Trust Region Sub-Optimal,GTRS),然后再利用二分算法获取精确解,进而缓解时钟偏差和周转时间(Turn-around Times,TATs)对定位精度的影响。实验数据表明,提出的TL-TW-TOA定位算法降低了计算复杂度,并减少了均方根误差(Root Mean Square Error,RMSE)。展开更多
A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off-...A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.展开更多
文摘Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.);these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part;similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite;compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 2<sup>2</sup> = 4 combination of controlling is done (i.e.);both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits.
文摘针对时钟偏差问题,提出基于双向到达时间(Two-way time of arrival,TW-ToA)测量的目标定位算法(Target Localization-based on TW-ToA,TL-TW-ToA)。TL-TW-TOA算法考虑了周转时间和时钟偏差问题。由于利用直接处理方法难以获取目标位置的最优解,TL-TW-TOA算法选用次优、强健算法进行近似,并将定位问题建立成广义信赖域次优问题(Generalized Trust Region Sub-Optimal,GTRS),然后再利用二分算法获取精确解,进而缓解时钟偏差和周转时间(Turn-around Times,TATs)对定位精度的影响。实验数据表明,提出的TL-TW-TOA定位算法降低了计算复杂度,并减少了均方根误差(Root Mean Square Error,RMSE)。
基金supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University.
文摘A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.
