A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate volt...A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage｜VGS｜p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages｜VGS｜n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages △VBE of bipolar junction transistors （BJTs）. The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 pprrd /℃ without trimming, over a temperature range from -40 to 120℃, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio （PSRR） is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2.展开更多
基金Project supported by the National Natural Science Foundation of China(No.61376032)
文摘A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage｜VGS｜p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages｜VGS｜n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages △VBE of bipolar junction transistors （BJTs）. The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 pprrd /℃ without trimming, over a temperature range from -40 to 120℃, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio （PSRR） is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2.
