In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the...In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.展开更多
In order to improve the drive current and subthreshold swing（SS）, a novel vertical-dual-source tunneling field-effect transistor（VDSTFET） device is proposed in this paper. The influence of source height, channel l...In order to improve the drive current and subthreshold swing（SS）, a novel vertical-dual-source tunneling field-effect transistor（VDSTFET） device is proposed in this paper. The influence of source height, channel length and channel thickness on the device are investigated through two-dimensional numerical simulations. Si-VDSTFET have greater tunneling area and thinner channel, showing an on-current as high as 1.24 A at gate voltage of 0.8 V and drain voltage of 0.5 V, off-current of less than 0.1 f A, an improved average subthreshold swing of 14 m V/dec,and a minimum point slope of 4 m V/dec.展开更多
基金supported by the Research Program of the National University of Defense Technology(Grant No.JC 13-06-04)
文摘In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.
基金Project supported by the National Natural Science Foundation of China(Nos.61204092,61574109)
文摘In order to improve the drive current and subthreshold swing（SS）, a novel vertical-dual-source tunneling field-effect transistor（VDSTFET） device is proposed in this paper. The influence of source height, channel length and channel thickness on the device are investigated through two-dimensional numerical simulations. Si-VDSTFET have greater tunneling area and thinner channel, showing an on-current as high as 1.24 A at gate voltage of 0.8 V and drain voltage of 0.5 V, off-current of less than 0.1 f A, an improved average subthreshold swing of 14 m V/dec,and a minimum point slope of 4 m V/dec.
