With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to co...With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.展开更多
This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. A...This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.展开更多
This paper presents an energy efficient architecture for successive approximation register(SAR)analog to digital converter(ADC).SAR ADCs with a capacitor array structure have been widely used because of its simple arc...This paper presents an energy efficient architecture for successive approximation register(SAR)analog to digital converter(ADC).SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed.However,conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits.The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor(CMOS)0.13 um library using Cadence Virtuoso design tool.Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3%compared with conventional SAR ADC,67%compared with the SAR ADC with split capacitor,and 35%compared with the resistor and capacitor(R&C)Hybrid SAR ADC.The ADC achieves an effective number of bits(ENOB)of 11.27 bits and consumes 61.7 uW at sampling rate of 2.56 MS/s,offering an energy consumption of 9.8 fJ per conversion step.The proposed SAR ADC offers 95.5%reduction in chip core area compared to conventional architecture,while occupying an active area of 0.088 mm2.展开更多
针对一阶噪声整形(NS)往往需要增加功耗而以较高的过采样比(OSR)来实现较高的有效位数(ENOB),提出了一种低OSR、低功耗的二阶无源NS SAR ADC。该无源NS模块较高的无源增益可以更好地抑制比较器的噪声;其残差电压是通过开关MOS阵列复用...针对一阶噪声整形(NS)往往需要增加功耗而以较高的过采样比(OSR)来实现较高的有效位数(ENOB),提出了一种低OSR、低功耗的二阶无源NS SAR ADC。该无源NS模块较高的无源增益可以更好地抑制比较器的噪声;其残差电压是通过开关MOS阵列复用积分电容实现采样,从而无需额外的残差采样电容,避免了残差采样电容清零和残差采样时kT/C噪声的产生,因此减小了总的kT/C噪声。180 nm CMOS工艺仿真结果表明,在不使用数字校准的情况下,所设计的10位二阶无源NS SAR ADC电路以100 kS/s的采样率和5的OSR,实现了13.5位ENOB,电路功耗仅为6.98μW。展开更多
针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损...针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。展开更多
为满足5.8 GHz雷达系统的需要,在HLMC55LP工艺中设计了一款12 bit SAR ADC,ADC的采样率为500 kHz/250 kHz两档可调,采用单调电容开关时序,且在电容阵列的高位部分加上2个冗余位设计,该冗余位对高位的CDAC建立误差,比较器误差都有一定的...为满足5.8 GHz雷达系统的需要,在HLMC55LP工艺中设计了一款12 bit SAR ADC,ADC的采样率为500 kHz/250 kHz两档可调,采用单调电容开关时序,且在电容阵列的高位部分加上2个冗余位设计,该冗余位对高位的CDAC建立误差,比较器误差都有一定的容忍能力,可以带来ADC性能上的提升。系统采用上极板采样,可以在采样周期结束的瞬间就开始逐位比较过程,省去了采用底极板采样第一拍CDAC建立的过程,提高了转换速度,相对于底极板采样也节省了一定的开关功耗。后仿结果表明,模拟输入20 kHz差分中频信号,在500 kHz采样频率,3.3 V电源电压下,ADC的有效位数为11.56 bit,SNR为71.04 dB,SFDR为80.37 dBc,功耗约为2 mW。展开更多
首先采用栅压自举采样电路、比较器、全差分分段式电容阵列以及同步时序控制来实现10 bit SAR ADC的设计,在此基础上加入Sigma-Delta调制器来实现噪声整形,并将动态比较器改为4输入动态比较器以便进行电压余量求和,最终实现了12 bit NS ...首先采用栅压自举采样电路、比较器、全差分分段式电容阵列以及同步时序控制来实现10 bit SAR ADC的设计,在此基础上加入Sigma-Delta调制器来实现噪声整形,并将动态比较器改为4输入动态比较器以便进行电压余量求和,最终实现了12 bit NS SAR ADC的设计。展开更多
针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器...针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器。采用55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证,测试结果表明,该ADC实现了34 dB SNDR、36 dB SFDR和1.6 GHz的模拟输入信号带宽。该ADC的版图面积为670μm×390μm,功耗为9.6 mW。展开更多
文摘With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.
基金supported in part by the National Natural Science Foundation of China under Grant No.61006027the New Century Excellent Talents Program of the Ministry of Education of China under Grant No.NCET-10-0297the Fundamental Research Funds for Central Universities under Grant No.ZYGX2012J003
文摘This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.
基金supported by Institute of Information&communications Technology Planning&Evaluation(IITP)grant funded by the Korea government(MSIT)(No.2020-0-01304,Development of Self-learnable Mobile Recursive Neural Network Processor Technology)also supported by the MSIT(Ministry of Science and ICT),Korea,under the Grand Information Technology Research Center support program(IITP-2020-0-01462)+3 种基金supervised by the IITP(Institute for Information&communications Technology Planning&Evaluation)”And also financially supported by the Ministry of Small and Medium-sized Enterprises(SMEs)and Startups(MSS),Korea,under the“Regional Specialized Industry Development Plus Program(R&D,S3091644)”supervised by the Korea Institute for Advancement of Technology(KIAT)supported by the AURI(Korea Association of University,Research institute and Industry)grant funded by the Korea Government(MSS:Ministry of SMEs and Startups).(No.S2929950,HRD program for 2020).
文摘This paper presents an energy efficient architecture for successive approximation register(SAR)analog to digital converter(ADC).SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed.However,conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits.The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor(CMOS)0.13 um library using Cadence Virtuoso design tool.Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3%compared with conventional SAR ADC,67%compared with the SAR ADC with split capacitor,and 35%compared with the resistor and capacitor(R&C)Hybrid SAR ADC.The ADC achieves an effective number of bits(ENOB)of 11.27 bits and consumes 61.7 uW at sampling rate of 2.56 MS/s,offering an energy consumption of 9.8 fJ per conversion step.The proposed SAR ADC offers 95.5%reduction in chip core area compared to conventional architecture,while occupying an active area of 0.088 mm2.
文摘针对一阶噪声整形(NS)往往需要增加功耗而以较高的过采样比(OSR)来实现较高的有效位数(ENOB),提出了一种低OSR、低功耗的二阶无源NS SAR ADC。该无源NS模块较高的无源增益可以更好地抑制比较器的噪声;其残差电压是通过开关MOS阵列复用积分电容实现采样,从而无需额外的残差采样电容,避免了残差采样电容清零和残差采样时kT/C噪声的产生,因此减小了总的kT/C噪声。180 nm CMOS工艺仿真结果表明,在不使用数字校准的情况下,所设计的10位二阶无源NS SAR ADC电路以100 kS/s的采样率和5的OSR,实现了13.5位ENOB,电路功耗仅为6.98μW。
文摘针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。
文摘针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器。采用55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证,测试结果表明,该ADC实现了34 dB SNDR、36 dB SFDR和1.6 GHz的模拟输入信号带宽。该ADC的版图面积为670μm×390μm,功耗为9.6 mW。
