With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to co...With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.展开更多
针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损...针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。展开更多
针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器...针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器。采用55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证,测试结果表明,该ADC实现了34 dB SNDR、36 dB SFDR和1.6 GHz的模拟输入信号带宽。该ADC的版图面积为670μm×390μm,功耗为9.6 mW。展开更多
为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提...为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm^2。ADC的微分非线性和积分非线性分别小于0.36最低有效位(LSB)和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 Msample/s。运行频率为230 Msample/s和260 Msample/s的ADC的功率消耗分别为13.9 m W和17.8 m W。展开更多
This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers. A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is cal...This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers. A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity. Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm. An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype, fabricated in UMC 0.18 um CMOS technology, achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s. The total power consumption is 0.918 mW for a 1.8 V supply, while the onchip reference consumes 53% of the total power. It achieves a figure of merit of 180 fJ/conv-step, excluding the reference＇s power consumption.展开更多
Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter(SAR ADC),a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size dig...Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter(SAR ADC),a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size digital calibration was proposed.The least mean square(LMS)calibration algorithm was employed with a ramp signal used as the calibration input.Weight errors,extracted under injected disturbances,underwent iterative training to optimize weight values.To address the trade-off between conversion accuracy and speed caused by a fixed step size,a novel variable step size algorithm tailored for SAR ADC calibration was proposed.The core circuit and layout of the SAR ADC were implemented using the Taiwan Semiconductor Manufacturing Company(TSMC)0.35μm complementary metal-oxide-semiconductor(CMOS)commercial process.Simulation of the SAR ADC calibration algorithm was conducted using Simulink,demonstrating quick convergence and meeting conversion accuracy requirements compared to fixed step size simulation.The results indicated that the convergence speed of the LMS digital calibration algorithm with variable step size was approximately eight times faster than that with a fixed step size,also yielding a lower mean square error(MSE).After calibration,the simulation results for the SAR ADC exhibited an effective number of bit(ENOB)of 11.79 bit and a signal-to-noise and distortion ratio(SNDR)of 72.72 dB,signifying a notable enhancement in the SAR ADC performance.展开更多
文摘With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.
文摘针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。
文摘针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器。采用55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证,测试结果表明,该ADC实现了34 dB SNDR、36 dB SFDR和1.6 GHz的模拟输入信号带宽。该ADC的版图面积为670μm×390μm,功耗为9.6 mW。
文摘为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm^2。ADC的微分非线性和积分非线性分别小于0.36最低有效位(LSB)和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 Msample/s。运行频率为230 Msample/s和260 Msample/s的ADC的功率消耗分别为13.9 m W和17.8 m W。
基金Project supported by the Major National Science & Technology Program of China(No.2010ZX03001-004-02)
文摘This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers. A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity. Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm. An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype, fabricated in UMC 0.18 um CMOS technology, achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s. The total power consumption is 0.918 mW for a 1.8 V supply, while the onchip reference consumes 53% of the total power. It achieves a figure of merit of 180 fJ/conv-step, excluding the reference＇s power consumption.
基金the Natural Science Basic Research Project of Shaanxi Province,China(2020JM-583)。
文摘Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter(SAR ADC),a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size digital calibration was proposed.The least mean square(LMS)calibration algorithm was employed with a ramp signal used as the calibration input.Weight errors,extracted under injected disturbances,underwent iterative training to optimize weight values.To address the trade-off between conversion accuracy and speed caused by a fixed step size,a novel variable step size algorithm tailored for SAR ADC calibration was proposed.The core circuit and layout of the SAR ADC were implemented using the Taiwan Semiconductor Manufacturing Company(TSMC)0.35μm complementary metal-oxide-semiconductor(CMOS)commercial process.Simulation of the SAR ADC calibration algorithm was conducted using Simulink,demonstrating quick convergence and meeting conversion accuracy requirements compared to fixed step size simulation.The results indicated that the convergence speed of the LMS digital calibration algorithm with variable step size was approximately eight times faster than that with a fixed step size,also yielding a lower mean square error(MSE).After calibration,the simulation results for the SAR ADC exhibited an effective number of bit(ENOB)of 11.79 bit and a signal-to-noise and distortion ratio(SNDR)of 72.72 dB,signifying a notable enhancement in the SAR ADC performance.
