For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from h...For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.展开更多
Recently,a generalized successive cancellation list(SCL)decoder implemented with shiftedpruning(SP)scheme,namely the SCL-SP-ωdecoder,is presented for polar codes,which is able to shift the pruning window at mostωtim...Recently,a generalized successive cancellation list(SCL)decoder implemented with shiftedpruning(SP)scheme,namely the SCL-SP-ωdecoder,is presented for polar codes,which is able to shift the pruning window at mostωtimes during each SCL re-decoding attempt to prevent the correct path from being eliminated.The candidate positions for applying the SP scheme are selected by a shifting metric based on the probability that the elimination occurs.However,the number of exponential/logarithm operations involved in the SCL-SP-ωdecoder grows linearly with the number of information bits and list size,which leads to high computational complexity.In this paper,we present a detailed analysis of the SCL-SP-ωdecoder in terms of the decoding performance and complexity,which unveils that the choice of the shifting metric is essential for improving the decoding performance and reducing the re-decoding attempts simultaneously.Then,we introduce a simplified metric derived from the path metric(PM)domain,and a custom-tailored deep learning(DL)network is further designed to enhance the efficiency of the proposed simplified metric.The proposed metrics are both free of transcendental functions and hence,are more hardware-friendly than the existing metrics.Simulation results show that the proposed DL-aided metric provides the best error correction performance as comparison with the state of the art.展开更多
Polar codes represent one of the major breakthroughs in 5G standard,and have been proven to be able to achieve the symmetric capacity of binary-input discrete memoryless channels using the successive cancellation list...Polar codes represent one of the major breakthroughs in 5G standard,and have been proven to be able to achieve the symmetric capacity of binary-input discrete memoryless channels using the successive cancellation list(SCL)decoding algorithm.However,the SCL algorithm suffers from a large amount of memory overhead.This paper proposes an adaptive simplified decoding algorithm for multiple cyclic redundancy check(CRC)polar codes.Simulation results show that the proposed method can reduce the decoding complexity and memory space.It can also acquire the performance gain in the low signal to noise ratio region.展开更多
In order to change the path candidates, reduce the average list size, and make more paths pass cyclic redundancy check （CRC）, multiple CRC-aided variable successive cancellation list （SCL） decoding algorithm is pr...In order to change the path candidates, reduce the average list size, and make more paths pass cyclic redundancy check （CRC）, multiple CRC-aided variable successive cancellation list （SCL） decoding algorithm is proposed. In the decoding algorithm, the whole unfrozen bits are divided into several parts and each part is concatenated with a corresponding CRC code, except the last part which is concatenated with a whole unfrozen CRC code. Each CRC detection is performed, and only those satisfying each part CRC become the path candidates. A variable list is setup for each part to reduce the time complexity. Variable list size is setup for each part to reduce the time complexity until one survival path in each part can pass its corresponding CRC. The results show that the proposed algorithm can reduce the average list size, and the frame error rate （FER） performance, and has a better performance with the increase of the part number.展开更多
通过信道极化,极化码理论上证明可渐进达到香农限。文中研究极化码在高斯信道下的串行抵消(successive cancellation,SC)译码算法,提出了一种基于整数操作的最小和译码算法。算法中信道输出值被均匀量化后再取整数,作为SC译码器的输入;...通过信道极化,极化码理论上证明可渐进达到香农限。文中研究极化码在高斯信道下的串行抵消(successive cancellation,SC)译码算法,提出了一种基于整数操作的最小和译码算法。算法中信道输出值被均匀量化后再取整数,作为SC译码器的输入;节点更新使用最小和算法,更新过程不需要量化操作,直接使用信道输出值量化后的整数值。数值仿真结果表明,在信噪比小于4 d B时,译码性能与基于浮点运算的原始SC译码一致;当误比特率为10-5时,提出的算法与原始SC译码的信噪比相差0.2 d B。所提出的算法便于硬件实现,运算中变量的大小都用8比特整数表示。展开更多
基金supported in part by the National Key R&D Program of China(No.2019YFB1803400)。
文摘For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.
基金supported in part by the National Key Research and Development Program of China under Grant 2018YFB1802303in part by the Zhejiang Provincial Natural Science Foundation of China under Grant LQ20F010010。
文摘Recently,a generalized successive cancellation list(SCL)decoder implemented with shiftedpruning(SP)scheme,namely the SCL-SP-ωdecoder,is presented for polar codes,which is able to shift the pruning window at mostωtimes during each SCL re-decoding attempt to prevent the correct path from being eliminated.The candidate positions for applying the SP scheme are selected by a shifting metric based on the probability that the elimination occurs.However,the number of exponential/logarithm operations involved in the SCL-SP-ωdecoder grows linearly with the number of information bits and list size,which leads to high computational complexity.In this paper,we present a detailed analysis of the SCL-SP-ωdecoder in terms of the decoding performance and complexity,which unveils that the choice of the shifting metric is essential for improving the decoding performance and reducing the re-decoding attempts simultaneously.Then,we introduce a simplified metric derived from the path metric(PM)domain,and a custom-tailored deep learning(DL)network is further designed to enhance the efficiency of the proposed simplified metric.The proposed metrics are both free of transcendental functions and hence,are more hardware-friendly than the existing metrics.Simulation results show that the proposed DL-aided metric provides the best error correction performance as comparison with the state of the art.
基金supported by the National Key R&D Program of China(2018YFB2101300)the National Science Foundation of China(61973056)
文摘Polar codes represent one of the major breakthroughs in 5G standard,and have been proven to be able to achieve the symmetric capacity of binary-input discrete memoryless channels using the successive cancellation list(SCL)decoding algorithm.However,the SCL algorithm suffers from a large amount of memory overhead.This paper proposes an adaptive simplified decoding algorithm for multiple cyclic redundancy check(CRC)polar codes.Simulation results show that the proposed method can reduce the decoding complexity and memory space.It can also acquire the performance gain in the low signal to noise ratio region.
基金supported by the National Natural Science Foundation of China (61475075,61271238)the Open Research Fund of Key Laboratory of Broadband Wireless Communication and Sensor Network Technology,Ministry of Education (NYKL2015011)
文摘In order to change the path candidates, reduce the average list size, and make more paths pass cyclic redundancy check （CRC）, multiple CRC-aided variable successive cancellation list （SCL） decoding algorithm is proposed. In the decoding algorithm, the whole unfrozen bits are divided into several parts and each part is concatenated with a corresponding CRC code, except the last part which is concatenated with a whole unfrozen CRC code. Each CRC detection is performed, and only those satisfying each part CRC become the path candidates. A variable list is setup for each part to reduce the time complexity. Variable list size is setup for each part to reduce the time complexity until one survival path in each part can pass its corresponding CRC. The results show that the proposed algorithm can reduce the average list size, and the frame error rate （FER） performance, and has a better performance with the increase of the part number.
文摘通过信道极化,极化码理论上证明可渐进达到香农限。文中研究极化码在高斯信道下的串行抵消(successive cancellation,SC)译码算法,提出了一种基于整数操作的最小和译码算法。算法中信道输出值被均匀量化后再取整数,作为SC译码器的输入;节点更新使用最小和算法,更新过程不需要量化操作,直接使用信道输出值量化后的整数值。数值仿真结果表明,在信噪比小于4 d B时,译码性能与基于浮点运算的原始SC译码一致;当误比特率为10-5时,提出的算法与原始SC译码的信噪比相差0.2 d B。所提出的算法便于硬件实现,运算中变量的大小都用8比特整数表示。
