New Lateral Super Junction MOSFETs with n^+-Floating Layer on High-Resistance Substrate

A new super junction LDMOST structure that suppresses the substrate-assisted depletion effect is designed with an n^＋-floating layer embedded in the high-resistance p-type substrate by implanting phosphor or arsenic. This effect results from a charge imbalance between the n-type and p-type pillars when the n-type pillars are depleted by p-type substrate. The high electric field around the drain is reduced by the n^＋-floating layer due to the REBULF effect,which causes the redistribution of the bulk electric field in the drift region,and thus the substrate supports more biases. The new structure features high breakdown voltage, low on-resistance,and charge balance in the drift region.

An oxide filled extended trench gate super junction MOSFET structure

This paper proposes an oxide filled extended trench gate super junction （SJ） MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication.

Investigations on mesa width design for 4H–SiC trench super junction Schottky diodes

Mesa width （WM） is a key design parameter for SiC super junction （SJ） Schottky diodes （SBD） fabricated by the trench-etching-and-sidewall-implant method. This paper carries out a comprehensive investigation on how the mesa width design determines the device electrical performances and how it affects the degree of performance degradation induced by process variations. It is found that structures designed with narrower mesa widths can tolerant substantially larger charge imbalance for a given BV target, but have poor specific on-resistances. On the contrary, structures with wider mesa widths have superior on-state performances but their breakdown voltages are more sensitive to p-type doping variation. Medium WM structures （-2 p.m） exhibit stronger robustness against the process variation resulting from SiC deep trench etching. Devices with 2-p.m mesa width were fabricated and electrically characterized. The fabricated SiC SJ SBDs have achieved a breakdown voltage of 1350 V with a specific on-resistance as low as 0.98 mΩ2.cm2. The estimated specific drift on- resistance by subtracting substrate resistance is well below the theoretical one-dimensional unipolar limit of SiC material. The robustness of the voltage blocking capability against trench dimension variations has also been experimentally verified for the proposed SiC SJ SBD devices.

A super junction SiGe low-loss fast switching power diode

This paper proposes a novel super junction （S J） SiGe switching power diode which has a columnar structure of alternating p- and n- doped pillar substituting conventional n- base region and has far thinner strained SiGe p＋ layer to overcome the drawbacks of existing Si switching power diode. The SJ SiGe diode can achieve low specific on-resistance, high breakdown voltages and fast switching speed. The results indicate that the forward voltage drop of SJ SiGe diode is much lower than that of conventional Si power diode when the operating current densities do not exceed 1000 A/cm^2, which is very good for getting lower operating loss. The forward voltage drop of the Si diode is 0.66V whereas that of the SJ SiGe diode is only 0.52V voltages are 203 V for the former and 235 V for the latter. at operating current density of 10A/cm^2. The breakdown Compared with the conventional Si power diode, the reverse recovery time of SJ SiGe diode with 20 per cent Ge content is shortened by above a half and the peak reverse current is reduced by over 15%. The SJ SiGe diode can remarkably improve the characteristics of power diode by combining the merits of both SJ structure and SiGe material.

基于C++SuperMix库的SIS混频器的研究

基于C++SuperMix软件库对680 GHz接收机中的双槽双超导隧道结(SIS)混频器进行深入模拟研究.在环境温度为4.2 K、本地振荡器(LO)频率为680 GHz、本振功率为100 nW、中频频率中心为10 GHz和中频匹配阻抗为50Ω的条件下,采用二次谐波的谐波平衡法,在0~500 K热噪声源温度下对SIS混频器的输出噪声温度进行建模仿真研究.计算得出:当偏置电压在2~3 mV变化时,SIS混频器的输出噪声温度均小于50 K,表明所研究的SIS混频器具有较好的噪声性能.

电荷非平衡super junction结构电场分布

建立了电荷非平衡情况下superjunction(SJ)耐压结构的二维电场分布理论模型.获得了浓度和宽度非平衡、梯形n-/p-区和横向线性缓变掺杂三种非平衡SJ结构的电场分布.理论分析结果与二维器件数值仿真软件MEDICI的仿真结果符合良好.虽然给出的电场分布为三角级数形式,但仍能从中获得很多重要信息.特别地,由此可求出非平衡SJ结构的峰值电场和耐压.该结果有助于对SJ结构的深入分析.

具有N型缓冲层REBULF Super Junction LDMOS

针对功率集成电路对低损耗LDMOS(lateral double-diffused MOSFET)类器件的要求,在N型缓冲层super junction LDMOS(buffered SJ-LDMOS)结构基础上,提出了一种具有N型缓冲层的REBULF(reduced BULk field)super junction LDMOS结构.这种结构不但消除了N沟道SJ-LDMOS由于P型衬底带来的衬底辅助耗尽效应问题,使super junction的N区和P区电荷完全补偿,而且同时利用REBULF的部分N型缓冲层电场调制效应,在表面电场分布中引入新的电场峰而使横向表面电场分布均匀,提高了器件的击穿电压.通过优化部分N型埋层的位置和参数,利用仿真软件ISE分析表明,新型REBULF SJ-LDMOS的击穿电压较一般LDMOS提高了49%左右,较文献提出的buffered SJ-LDMOS结构提高了30%左右.

A novel TFS-IGBT with a super junction floating layer

A novel trench field stop（TFS） IGBT with a super junction（SJ） floating layer（SJ TFS-IGBT） is proposed. This IGBT presents a high blocking voltage（〉 1200 V）,low on-state voltage drop and fast turn-off capability.A SJ floating layer with a high doping concentration introduces a new electric field peak at the anode side and optimizes carrier distribution,which will improve the breakdown voltage in the off-state and decrease the energy loss in the on-state /switching state for the SJ TFS-IGBT.A low on-state voltage（VF） and a high breakdown voltage（BV） can be achieved by increasing the thickness of the SJ floating layer under the condition of exact charge balance.A low turn-off loss can be achieved by decreasing the concentration of the P-anode.Simulation results show that the BV is enhanced by 100 V,VF is decreased by 0.33 V（at 100 A/cm2） and the turn-off time is shortened by 60%,compared with conventional TFS-IGBTs.

Super junction LDMOS with enhanced dielectric layer electric field for high breakdown voltage

The lateral super junction （SJ） power devices suffer the substrate-assisted depletion （SAD） effect, which breaks the charge balance of SJ resulting in the low breakdown voltage （BV）. A solution based on enhancing the electric field of the dielectric buried layer is investigated for improving the BV of super junction LDMOSFET （SJ-LDMOS）. High density interface charges enhance the electric field in the buried oxide （BOX） layer to increase the block voltage of BOX, which suppresses the SAD effect to achieve the charge balance of SJ. In order to obtain the linear enhancement of electric field, SO1 SJ-LDMOS with trenched BOX is presented. Because the trenched BOX self-adaptively collects holes according to the variable electric field strength, the approximate linear charge distribution is formed on the surface of the BOX to enhance the electric field according to the need. As a result, the charge balance between N and P pillars of SJ is achieved, which improves the BV of SJ-LDMOS to close that of the idea SJ structure.

A novel multiple super junction power device structure with low specific on-resistance

A novel multiple super junction （MS J） LDMOS power device is proposed to decrease Ron due to lateral and vertical interactions between the N-pillar and P-pillar. In the studied device： multiple layers of SJ are introduced oppositely under surface S J; when compared with 2D-depleting of the conventional super junction （CSJ）, a 3D- depleted effect is formed in the MSJ thanks to vertical electric field modulation; and, current distribution is improved by deep drain, which increases the drift doping concentration and results in a lower on-resistance. The high electric field around the drain region by substrate-assisted depleted effect is reduced due to the charge balance result from the electric field shielding effect of the bottom S J, which causes the uniform electric field in the drift region and the high breakdown voltage. The numerical simulation results indicate that the specific on-resistance of the MSJ device is reduced by 42% compared with that of CSJ device, while maintaining a high breakdown voltage; the cell pitch of the device is 12 μm.

Concept and design of super junction devices

The super junction（SJ） has been recognized as the ＂milestone＂ of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer（VSL）. The basic structure of the SJ is a typical junction-type VSL（J-VSL） with the periodic N and P regions. However, the conventional VSL is a typical resistance-type VSL（R-VSL） with only an N or P region. It is a qualitative change of the VSL from the R-VSL to the JVSL, introducing the bulk depletion to increase the doping concentration and optimize the bulk electric field of the SJ. This paper firstly summarizes the development of the SJ, and then the optimization theory of the SJ is discussed for both the vertical and the lateral devices, including the non-full depletion mode, the minimum specific on-resistance optimization method and the equivalent substrate model. The SJ concept breaks the conventional＂silicon limit＂ relationship of R_（on）∝V_B^（2.5）, showing a quasi-linear relationship of R_（on）∝V_B^（1.03）.

A Novel Super-junction LDMOST Concept with Split p Columns

In this paper, we propose a novel low on-resistance Super Junction （S J） Lateral Double-diffusion MOSFET （LDMOST） which has split p column structures with rated voltage of 60-100V. The key feature of this new structure is that the split p column super junction primarily provides the low on-resistance path and it just locates at the surface of the drift region rather than the entire drift region. The manufacturing process of the device is relatively simple and is compatible with the Bi-CMOS process. Three dimension device simulations indicate that this structure can achieve a low specific on-resistance of 11.5 mΩ·cm^2 at a gate voltage of 5 V compared with 27.7 mΩ·cm^2 for the conventional LDMOST at the breakdown voltage of 80V.

High-voltage super-junction lateral double-diffused metal-oxide semiconductor with a partial lightly doped pillar

A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.

New CMOS compatible super-junction LDMOST with n-type buried layer

A new super-junction lateral double diffused MOSFET （LDMOST） structure is designed with n-type charge compensation layer embedded in the p^--substrate near the drain to suppress substrate-assisted depletion effect that results from the compensating charges imbalance between the pillars in the n-type buried layer. A high electric field peak is introduced in the surface by the pn junction between the p^--substrate and n-type buried layer, which given rise to a more uniform surface electric field distribution by modulation effect. The effect of reduced bulk field （REBULF） is introduced to improve the vertical breakdown voltage by reducing the high bulk electric field around the drain, The new structure features high breakdown voltage, low on-resistance and charges balance in the drift region due to n-type buried layer.

1500 V超结功率MOS器件优化与电容特性研究

本文利用半超结结构进行高压超结功率金属氧化物半导体(Metal Oxide Semiconductor,MOS)器件的设计,基于Sentaurus TCAD(Technology Computer Aided Design)仿真平台设计超结元胞结构并优化高压超结功率MOS器件的击穿电压与导通电阻,随后探究了寄生电容的特性.最后,基于多次外延工艺自主设计出一款器件结构仿真击穿电压1658 V、工艺仿真击穿电压1598 V、比导通电阻值303 mΩ·cm^(2)的高压超结功率MOS器件,与相同耐压值器件相比,比导通电阻值下降约50%.同时探究了超结掺杂浓度与厚度以及电压支持层掺杂浓度与厚度4个主要结构参数对器件寄生电容特性的影响.

基于电荷耦合效应的超级结JBS二极管的仿真分析

为提升现代单极型功率二极管的性能,进一步突破“硅极限”,通过加大传统JBS二极管中P+区结深,引入超级结结构以减薄芯片厚度,缓解传统单极型器件通态压降与反向阻断电压之间的矛盾,提高单位面积器件的导通电流密度。使用数值方法分析了超级结JBS二极管中P柱区浓度、N柱区宽度和N柱区浓度对正向导通特性以及反向阻断特性的影响,应用电场耦合效应理论分析了超级结JBS二极管的正向导通和反向阻断机理,设计了一款300 V的超级结JBS二极管。

嵌入分段半超结的p-栅增强型垂直GaN基HFET

元胞面积相同的增强型垂直GaN/AlGaN异质结场效应管比横向HFET能承受更高的电压和更大的电流,适用于大功率领域,但在耐压时漂移区场强峰值高而容易提前击穿。提出了一种嵌入分段半超结的增强型垂直HFET,利用p型掺杂GaN栅和p+型掺杂GaN电流阻挡层抬高GaN/AlGaN异质结导带至费米能级之上,在栅压为0时夹断异质结的2DEG沟道,实现增强功能;在漂移区两侧插入2段p-GaN柱,形成p/n/p型离散半超结,改善电场均匀性。采用Silvaco TCAD软件模拟了Al组份、CBL浓度、p-GaN柱的宽度和厚度等参数对器件性能的影响。结果表明,相比于包含普通半超结的HFET,器件的击穿电压提升了8.67%,静态品质因数提升了11.25%,导通延时缩短了16.38%,关断延时缩短了3.80%,可为设计高性能HFET提供新思路。

基于深沟槽单次外延工艺超级结MOS器件耐压提升与优化

介绍了超级结MOS器件的一种主流工艺—深沟槽单次外延工艺,详细介绍了该工艺的工艺流程及特点。基于超级结MOS器件的电荷平衡原理,分析不同P柱浓度条件下器件击穿电压(Breakdown Voltage)的变化规律,揭示击穿电压(BV)偏低的原因,提出一种改善方案,最终通过实验验证该方案的可行性。

SiC超结MOSFET的短路特性研究

SiC超结MOSFET设计基于N/P柱的电荷补偿效应,在保证耐压的同时具有较低的导通损耗和更快的开关速度,因此对SiC超结MOSFET可靠性的分析研究有助于深入理解器件工作机理,为更好地应用提供必要的理论支撑。基于TCAD Sentaurus模拟软件,对1200 V电压等级的传统SiC MOSFET结构和SiC超结MOSFET结构进行建模。首先对比了2种器件的基本电学参数,然后重点分析了短路特性差异,在相同短路条件下对器件内部的物理机理进行了分析。结果表明SiC超结MOSFET可以有效地提高器件的击穿电压和导通电阻,同时表现出更好的短路可靠性。进一步分析了不同的偏置电压下SiC超结MOSFET的短路特性,结果表明,随着外部施加偏置电压增加,器件的短路耐受时间减小,同时短路饱和电流也会相应增大。

Si/SiC超结LDMOSFET的短路和温度特性

Si/SiC超结横向双扩散金属氧化物半导体场效应管(SJ-LDMOSFET)能有效改善Si SJ-LDMOSFET阻断电压低、温度特性差和短路可靠性低的问题。采用TCAD软件对Si SJ-LDMOSFET和Si/SiC SJ-LDMOSFET的短路和温度特性进行研究。当环境温度从300 K上升到400 K时,Si/SiC SJ-LDMOSFET内部最高温度均低于Si SJ-LDMOSFET,表现出良好的抑制自热效应的能力;Si/SiC SJ-LDMOSFET的击穿电压基本保持不变,且饱和电流退化率较低。发生短路时,Si/SiC SJ-LDMOSFET内部最高温度上升率要明显小于Si SJ-LDMOSFET。在环境温度为300 K和400 K时,Si/SiC SJ-LDMOSFET的短路维持时间相对于Si SJ-LDMOSFET分别增加了230%和266.7%。研究结果显示Si/SiC SJ-LDMOSFET在高温下具有更好的温度稳定性和抗短路能力,适用于高温、高压和高短路可靠性要求的环境中。