A Design of the Elliptic Switched Current Filter

In conformity with a fifth order RLC elliptic filter circuit prototype, it is easy to conceive the corresponding RC active filter circuit. Simple and feasible method presented here can be used to contrive the equivalent switched capacitor filter circuit and switched current filter circuit. Consulting the technique data manual, we can expediently design a specific RLC filter. Therefore, it is of great convenience to design the switched current filter, which has the same performances. Such a kind of technology is useful in the domain of analogue sampled data signal processing.

Switching of Capacitors in an Asymmetric Induction Motor with Single-Phase Power,Triggering Several Applied Loads

xThis study has as its objective to collaborate with the expansion in the market of electric energy in rural areas,offering as such an innovative prospect to the solution of associated problems through use of the asymmetric three-phase induction motor,supplied by a single-phase source.In this system,capacitor switching is applied during operation,while theoretical and practical results are presented for the application of this switching in a three-phase asymmetric induction motor of 20 hp.

A Novel Dual-Rate Sampling Switched-Capacitor Configuration and Its Application

In order to realize accurate bilinear transformation from s- to z-domain,a novelswitched-capacitor configuration is proposed in the light of principles of dual-rate sampling and chargeconservation,which has also been used for building a 5th-order elliptic lowpass filter.The filter issimulated and measured in typical 0.34 μm/3.3 V Si CMOS process models,special full differentialoperational amplifiers and CMOS transfer gate switches,which achieves 80 MHz sampling rate,17.8MHz cutoff frequency,0.052 dB maximum passband ripple,42.1 dB minimum stopband attenuation and74 mW quiescent power dissipation.At the same time,the dual-rate sampling topology breaks thetraditional restrictions of filter introduced by unit-gain bandwidth and slew rate of operational amplifiersand also improves effectively their performances in high-frequency applications.It has been applied forthe design of an anti-alias filter in analog front-end of video decoder IC with 15 MHz signal frequencyyet.

Genetic Algorithm Based 7-Level Step-Up Inverter with Reduced Harmonics and Switching Devices

This paper presents a unique voltage-raising topology for a single-phase seven-level inverter with triple output voltage gain using single input source and two switched capacitors.The output voltage has been boosted up to three times the value of input voltage by configuring the switched capacitors in series and parallel combinations which eliminates the use of additional step-up converters and transformers.The selective harmonic elimination(SHE)approach is used to remove the lower-order harmonics.The optimal switching angles for SHE is determined using the genetic algorithm.These switching angles are com-bined with a level-shifted pulse width modulation(PWM)technique for pulse generation,resulting in reduced total harmonic distortion(THD).A detailed com-parison has been made against other relevant seven-level inverter topologies in terms of the number of switches,drivers,diodes,capacitors,and boosting facil-ities to emphasize the benefits of the proposed model.The proposed topology is simulated using MATLAB/SIMULINK and an experimental prototype has been developed to validate the results.The Digital Signal Processing(DSP)TMS320F2812 board is used to generate the switching pulses for the proposed technique and the experimental results concur with the simulated model outputs.

Composite Converter Combined APFC with Switched-capacitor Converter

To reduce switch numbers and voltage stress in semiconductor devices,this paper proposes a novel single-phase converter combined Active Power Factor Correction(APFC)with switched-capacitor converter.In addition,dynamic voltage regulation and voltage gain are improved by integrating the boost converter and switching capacitor cells.The interstage bulk capacitor is no longer needed.An average current control with redistribution of voltage in cells is proposed to obtain voltage lift ability of the switching capacitor cells and maintain a high-power factor.To study and verify the proposed converter preliminarily,theoretical analysis and simulation are presented in the paper.Furthermore,a 50o W prototype with two different configurations is built for experimental verification.The proposed converter can reach 95.62%of maximum efficiency,0.99 of power factor,and 3.55%of THD with 600 V output voltage,simultaneously.

A Novel Single Switch High Gain DC-DC Converter Topology for Renewable Energy Systems

Renewable energy with sources such as photovoltaic(PV)or fuel cells can be utilized for the generation of elec-trical power.But these sources generate fewer voltage values and therefore require high gain converters to match with DC bus voltage in microgrids.These high gain converters can be implemented with switched capacitors to meet the required DC bus voltage.Switched capacitors operate in a series and parallel combination during switch-ing operation and produce high static gain,limits reverse voltage that appears across the components.A novel converter is proposed that satisfies all the features such as high voltage gain,only one switch,forces less potential stress cross the components,ripple current is less.These features of the proposed converter are verified through MATLAB/SIMULINK.

Overall optimization of distribution networks

Network reconfiguration and capacitor switching are important measures to reduce power loss and improve security and economy in automation of distribution. A new method based on parallel genetic algorithm is proposed to search the whole problem space for better solution. Multiple populations evolve independently and communicate periodically, which simulates parallel computing process to save computing time. The results show that the method is robust and has better benefit than the alterative iteration method. In addition, the effect of overall optimization is better than optimization alone. Power loss can be reduced and the level of voltage can be greatly improved.

Non-isolated Step-up DC-DC Converter Based on Switched Capacitor Cells

A non-isolated high gain step-up DC-DC converter for low power applications is suggested in this study.In the designed transformerless converter,the main switch current and voltage stress is reduced while maintaining high voltage gain.For instance,with a duty cycle of 0.5 a voltage gain equal to 5 is achieved while the normalized switch voltage stress is 0.4.Also,it decreases power losses of active and passive elements.In the proposed converter design,the switched-capacitor(SC)technique is used to obtain maximum voltage transfer gain using only one switch.The three modes of operation,i.e.,continuous conduction mode(CCM),boundary conduction mode(BCM),and discontinuous conduction mode(DCM),are studied in detail.The small signal analysis(SSA)of the designed converter is investigated,and its steady-state model is examined under CCM.Performance of the proposed converter proposed in this study is assessed and tested using a prototype.Efficiency of the converter is recorded above 94%in a wide range of output powers.Overall,compared to the other converters,the results suggest satisfactory performance of the designed converter.An issue of the proposed converter is that its input current is not smooth due to using the switched-capacitor cell in its structure.This issue is alleviated by using input filters.

Capacitor Pattern H-Bridge Multilevel Inverter (CPHMLI) Using Phase Diposition Pulse Width Modulation for Grid Applications

This work presents an implementation of an innovative single phase multilevel inverter using capacitors with reduced switches. The proposed Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology consists of a proper number of Capacitor connected with switches and power sources. The advanced switching control supplied by Pulse Width Modulation (PDPWM) to attain mixed staircase switching state. The charging and discharging mode are achieved by calculating the voltage error at the load. Furthermore, to accomplish the higher voltage levels at the output with less number of semiconductors switches and simple commutation designed using CPHMLI topology. To prove the performance and effectiveness of the proposed approach, a set of experiments performed under various load conditions using MATLAB tool.

A multifunctional switched-capacitor programmable gain amplifier for high-definition video analog front-ends

A multifunctional programmable gain amplifier（PGA） that provides gain and offset adjusting abilities for high-definition video analog front-ends（AFE） is presented. With a switched-capacitor structure, the PGA also acts as a sample and holder of the analog-to-digital converter（ADC） in the AFE to reduce the power consumption and chip area of the whole AFE. Furthermore, the PGA converts the single-ended video signal into differential signal for the following ADC to reject common-mode noise and interferences. The 9-bit digital-to-analog converter（DAC） for gain and offset adjusting is embedded into the switched capacitor networks of the PGA. A video AFE integrated circuit based on the proposed PGA is fabricated in a 0.18- m process. Simulation and measurement results show that the PGA achieves a gain control range of 0.90 to 2.34 and an offset control range of –220 to220 mV while consuming 10.1 mA from a 1.8 V power supply.

Generalized Switched-Capacitor Step-up Multilevel Inverter Employing Single DC Source

In this paper,a new generalized step-up multilevel DC-AC converter is proposed,which is suitable for applications with low-voltage input sources,such as photovoltaic power generation and electric vehicles.This inverter can achieve a high voltage gain by controlling the series-parallel conversion of the DC power supply and capacitors.Only one DC voltage source and a few power devices are employed.The maximum output voltage and the number of output levels can be further increased through the switched-capacitor unit’s extension and the submodule cascaded extension.Moreover,the capacitor voltages are self-balanced without complicated voltage control circuits.The complementary operating mechanism between each pair of switches simplifies the modulation algorithm.The inductiveload ability is fully taken into account in the proposed inverter.Additionally,a remarkable characteristic of the inverter is that the charging and discharging states among different capacitors are synchronous,which reduces the voltage ripple of the frontend capacitors.The circuit structure,the working principle,the modulation strategy,the capacitors and losses analysis are presented in detail.Afterwards,the advantages of the proposed inverter are analyzed by comparing with other recently proposed inverters.Finally,the steady-state and dynamic performance of the proposed inverter is verified and validated by simulation and experiment.

A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator（VCO） with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between -118.5 dBc/Hz and -122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the tuning range is analyzed and derived in terms of design parameters,yielding useful equations to guide the circuit design.

Non-ideal effects of MOS capacitor in a switched capacitor waveform recorder ASIC

SCAs （Switched Capacitor Arrays） have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents （~ 4 mA max） and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 mW/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 mV with 625 kHz full-scale sine wave as input, sampling at 40 MSPS （Mega-samples per Second） and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 mV. The test results validate the feasibility of the MOS capacitor.

A Switched Capacitor Harmonic Compensation Part for Switching Supplies

A new approach based on switched capacitor network to harmonic compensation for switching supplies is presented in the paper. The basic principle is discussed. SPICE simulation is applied to analyze the behaviour of the switched capacitor harmonic compensation part.

A novel switched capacitor bandgap reference with a correlated double sampling structure

A switched capacitor bandgap voltage reference with correlated double sampling structure embedded in a temperature sensor is implemented in a standard 0.35 um CMOS process. Due to the smaller change of the op-amp＇s output voltage, this topology is very suitable for low power applications. In addition, errors caused by the finite op-amp gain, input offset voltage, and 1/f noise are eliminated with the correlated double sampling technique. Additionally, two-level process calibration techniques are designed to minimize the process spread. Finally, a method of getting a full period valid reference voltage output is discussed and experimental results are provided to verify the effectiveness of the proposed structure.

Compact DC-DC Converter for Pocket Micro-Controller Systems

Novel compact DC-DC converters for pocket micro-controller systems are discussed in the paper, which are based on switched capacitors and inductorless,consequently are more suitable for being hybridized. The new converters en-able the pocket microcontroller system to be powered by only one +12V source,while +5V and -12V are converted from the +12V source. The basic princi-ple, voltage ratio, efficiency and ripples are analysed. Experiment and SPICE simulation are also given, which show positive results.

Impact of FACTS devices on exercising market power in deregulated electricity market

In power system studies, congestion in trans- mission lines and utilization of flexible alternating current transmission system （FACTS） devices are closely associated. These devices are very important due to their role in power delivery system enhancement. It is to be noted that the generation companies can exercise their market power which depends on the line flows, line constraints, generators＇ location and its share to the individual loads. This issue cannot be overlooked as it creates monopoliness which is against the deregulated market policy. The objective of this paper is to study the impact of market power when FACTS devices like thyristor controlled switching capacitor （TCSC） and thyristor controlled phase angle regulator （TCPAR） are used under steady state operation. The market power is determined using nodal must-run share （NMRS） index for the standard IEEE 14- bus system with and without the above FACTS devices and the results obtained are compared. All the above simula- tions are conducted in a MATLAB 7.9-R2009b environment.

A novel CMOS charge-pump circuit with current mode control 110mA at 2.7V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm^2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.

A Photovoltaic Generation System Based on Wide Voltage-Gain DC-DC Converter and Differential Power Processors for DC Microgrids

In this paper,a photovoltaic(PV)generation system based on front-stage differential power processors(DPP)and BACK-stage centralized wide voltage-gain converter is proposed.The resonant switched capacitor(ReSC)converter,which features high power density and high efficiency,is employed as the differential power processor and aims at processing the differential power among series-connected PV modules,avoiding the great power loss caused by power mismatch of PV modules.The ReSC converter in PV system can operate in equalization mode or MPPT mode and both modes are researched.The BACK-stage DC-DC converter is implemented as the dual-phase-shift controlled full-bridge converter(DPS-FBC).It has high conversion efficiency and wide voltage gain,suitable for PV generation applications.The current source control for grid-connected mode and the voltage source control for islanding mode are developed for DPS-FBC.Therefore,for the whole system with front and BACK stage converters,the dual-mode control strategy is proposed.When the system is connected to the grid,DPS-FBC operates as the current source for global MPPT for PV modules while ReSC converters operate in maximum power point tracking(MPPT)mode for local MPPT.When the system operates in an island,DPS-FBC works as the voltage source for constant output voltage control and ReSC converters work in equalization mode.The mode switch is based on the voltage of output DC bus.Simulations and experiments verify the feasibility of the proposed PV generation system and the effectiveness of the proposed control algorithm.

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.