In this study,a compact 16-channel integrated charge-sensitive preamplifier named the smart preamplifier(SPA)was developed to support the large-scale detector array used in modern nuclear physics experiments.Two types...In this study,a compact 16-channel integrated charge-sensitive preamplifier named the smart preamplifier(SPA)was developed to support the large-scale detector array used in modern nuclear physics experiments.Two types of SPA,namely SPA02 and SPA03(with external field effect transistor),have been manufactured to match silicon detectors with small and large capacitances,respectively.The characteristics of the SPA include fast response of typically less than 6 ns for pulse rising time and low equivalent noise of 1.5 keV at zero input capacitance.The energy sensitivity and pulse decay time can be easily adjusted by changing the feedback capacitance Cfand resistance Rfin various applications.A good energy resolution of 24.4 keV for 5.803-MeV alpha particles from 244 Cm was achieved using a small-sized Si-PIN detector;for the silicon strip detectors in the test with the alpha source,a typical energy resolution of 0.6–0.8%was achieved.The integrated SPA has been employed in several experiments of silicon strip detectors with hundreds of channels,and a good performance has been realized.展开更多
In this paper, the design and analysis of a new low noise charge sensitive preamplifier for silicon strip, Si(Li), CdZnTe and CsI detectors etc. with switch control feedback resistance were described, the entire syste...In this paper, the design and analysis of a new low noise charge sensitive preamplifier for silicon strip, Si(Li), CdZnTe and CsI detectors etc. with switch control feedback resistance were described, the entire system to be built using the CMOS transistors. The circuit configuration of the CSP proposed in this paper can be adopted to develop CMOS-based Application Specific Integrated Circuit further for Front End Electronics of read-out system of nuclear physics, particle physics and astrophysics research, etc. This work is an implemented design that we succeed after a simulation to obtain a rise time less than 3ns, the output resistance less than 94? and the linearity almost good.展开更多
设计出了一种用于光强检测的前置放大及量程自动转换电路。许多光强信号放大电路仅追求高增益,忽略了对测量范围的考虑。本文采用同轴尾纤型光电探测器把光强信号转换成光电流信号,精密截波稳定型运算放大器ICL7652把光电流信号转化为...设计出了一种用于光强检测的前置放大及量程自动转换电路。许多光强信号放大电路仅追求高增益,忽略了对测量范围的考虑。本文采用同轴尾纤型光电探测器把光强信号转换成光电流信号,精密截波稳定型运算放大器ICL7652把光电流信号转化为电压信号,量程转换电路74HC4052受单片机控制可在4个量程之间自动转换,通过调节暗电流补偿电路减小光电二极管暗电流所产生的影响。仿真测试结果表明,电路参数选择合理、电路模块性能稳定,并且很好地降低了噪声的影响,设计的电路具有低噪声、高增益、高共模抑制比、失调小等优点,探测光强动态范围可达76 d B。展开更多
An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and...An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to 〈 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.展开更多
A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4thorde...A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4thorder Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter （SAR ADC）, and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 μS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.展开更多
基金supported by the National Key R&D Program of China(No.2018YFA0404404)the National Natural Science Foundation of China(Nos.11635015,U1732145,11705285,11805280,U1867212,and 11961131012)the Continuous Basic Scientific Research Project(No.WDJC-2019-13).
文摘In this study,a compact 16-channel integrated charge-sensitive preamplifier named the smart preamplifier(SPA)was developed to support the large-scale detector array used in modern nuclear physics experiments.Two types of SPA,namely SPA02 and SPA03(with external field effect transistor),have been manufactured to match silicon detectors with small and large capacitances,respectively.The characteristics of the SPA include fast response of typically less than 6 ns for pulse rising time and low equivalent noise of 1.5 keV at zero input capacitance.The energy sensitivity and pulse decay time can be easily adjusted by changing the feedback capacitance Cfand resistance Rfin various applications.A good energy resolution of 24.4 keV for 5.803-MeV alpha particles from 244 Cm was achieved using a small-sized Si-PIN detector;for the silicon strip detectors in the test with the alpha source,a typical energy resolution of 0.6–0.8%was achieved.The integrated SPA has been employed in several experiments of silicon strip detectors with hundreds of channels,and a good performance has been realized.
基金Supported in part by the Third World Academy of Sciences, in part by the Institute of Modern Physics, Chinese Academy of Sciencesin part by the National Natural Science Foundation of China (10675153)
文摘In this paper, the design and analysis of a new low noise charge sensitive preamplifier for silicon strip, Si(Li), CdZnTe and CsI detectors etc. with switch control feedback resistance were described, the entire system to be built using the CMOS transistors. The circuit configuration of the CSP proposed in this paper can be adopted to develop CMOS-based Application Specific Integrated Circuit further for Front End Electronics of read-out system of nuclear physics, particle physics and astrophysics research, etc. This work is an implemented design that we succeed after a simulation to obtain a rise time less than 3ns, the output resistance less than 94? and the linearity almost good.
文摘设计出了一种用于光强检测的前置放大及量程自动转换电路。许多光强信号放大电路仅追求高增益,忽略了对测量范围的考虑。本文采用同轴尾纤型光电探测器把光强信号转换成光电流信号,精密截波稳定型运算放大器ICL7652把光电流信号转化为电压信号,量程转换电路74HC4052受单片机控制可在4个量程之间自动转换,通过调节暗电流补偿电路减小光电二极管暗电流所产生的影响。仿真测试结果表明,电路参数选择合理、电路模块性能稳定,并且很好地降低了噪声的影响,设计的电路具有低噪声、高增益、高共模抑制比、失调小等优点,探测光强动态范围可达76 d B。
基金Project supported by the National Natural science Foundation of China(Nos.60725415,60971066)
文摘An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to 〈 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.
基金supported by the National Basic Research Program of China(No.2011CB933203)the National Natural Science Foundation of China(Nos.61076023,61178051)the National High Technology Research & Development Program of China(No.2012AA030608)
文摘A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4thorder Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter （SAR ADC）, and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 μS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.
